Patrick Ong

InGaAs Gate-All-Around Nanowire Devices on 300mm Si Substrates

In this letter, we present the first InGaAs gate-all-around (GAA) nanowire devices fabricated on 300mm Si substrates. For an L_G of 60 nm an extrinsic g_m of 1030 μS/μm at V_ds = 0.5 V is achieved which is a 1.75× increase compared with the replacement fin FinFet process. This improvement is attributed to the elimination of Mg counterdoping in the GAA flow. Ultrascaled nanowires with diameters of 6 nm were demonstrated to show immunity to D_it resulting in an SS_SAT of 66 mV/decade and negligible drain-induced barrier lowering for 85-nm L_G devices.

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

InGaAs FinFETs fabricated by an unique Si fin replacement process have been demonstrated on 300mm Si substrates. The devices are integrated by process modules developed for a Si-IIIV hybrid 300mm R&D pilot line, compatible for future CMOS high-volume manufacturing. First devices with a SS of 190 mV/dec and extrinsic gm of 558 μS/μm are achieved for an EOT of 1.9nm, Lg of 50nm and fin width of 55nm. A trade-off between off state leakage and mobility for different p-type doping levels of the InP and InGaAs layers is found and the RMG high-κ last processing is demonstrated to offer significant performance improvements over that of high-κ first.

A 400GHz f MAX fully self-aligned SiGe:C HBT architecture

An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An fMAX value of 400GHz is reached by structural as well as intrinsic advancements made to the HBT device.

Integration of III-V on Si for High-Mobility CMOS

In this paper we present results from an InGaAs/InP implant free quantum well device integrated fully in a Si CMOS processing line. The virtual InP substrates are generated using a Si template which is prepared by standard STI processing. The Si in the STI trenches is etched and a Ge seed layer grown.

Electrical Characteristics of p-Type Bulk Si Fin Field-Effect Transistor Using Solid-Source Doping With 1-nm Phosphosilicate Glass

For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this letter, solid-source doping for channel doping using 1-nm phosphosilicate glass was demonstrated on both p-type (100) Si substrate and p-type bulk Si FinFET. The profile of phosphorus in p-type (100) Si substrate was analyzed by secondary ion mass spectrometry and it was diffused deeper with higher thermal budget of anneal. Fabricated bulk Si FinFETs with using 1-nm phosphosilicate glass showed threshold voltage shift with several anneals at 1-μm and 70-nm gate lengths. Hole mobility at 1-μm gate length and transconductance at 70-nm gate length were also reduced due to increase in impurity concentration of phosphorus diffused by anneals into Fins. Phosphorus diffusion into Fins with using 1-nm phosphosilicate glass was investigated and phosphorus behavior after anneal was clarified by electrical data of p-type bulk Si FinFETs.

193nm immersion lithography for high-performance silicon photonic circuits

Large-scale photonics integration has been proposed for many years to support the ever increasing requirements for long and short distance communications as well as package-to-package interconnects. Amongst the various technology options, silicon photonics has imposed itself as a promising candidate, relying on CMOS fabrication processes. While silicon photonics can share the technology platform developed for advanced CMOS devices it has specific dimension control requirements. Though the device dimensions are in the order of the wavelength of light used, the tolerance allowed can be less than 1% for certain devices. Achieving this is a challenging task which requires advanced patterning techniques along with process control. Another challenge is identifying an overlapping process window for diverse pattern densities and orientations on a single layer. In this paper, we present key technology challenges faced when using optical lithography for silicon photonics and advantages of using the 193nm immersion lithography system. We report successful demonstration of a modified 28nm- STI-like patterning platform for silicon photonics in 300mm Silicon-On-Insulator wafer technology. By careful process design, within-wafer CD variation (1sigma) of <1% is achieved for both isolated (waveguides) and dense (grating) patterns in silicon. In addition to dimensional control, low sidewall roughness is a crucial to achieve low scattering loss in the waveguides. With this platform, optical propagation loss as low as ~0.7 dB/cm is achieved for high-confinement single mode waveguides (450x220nm). This is an improvement of >20 % from the best propagation loss reported for this cross-section fabricated using e-beam lithography. By using a single-mode low-confinement waveguide geometry the loss is further reduced to ~0.12 dB/cm. Secondly, we present improvement in within-device phase error in wavelength selective devices, a critical parameter which is a direct measure of line-width uniformity improvement due to the 193nm immersion system. In addition to these superior device performances, the platform opens scenarios for designing new device concepts using sub-wavelength features. By taking advantage of this, we demonstrate a cost-effective robust single-etch sub-wavelength structure based fiber-chip coupler with a coupling efficiency of 40 % and high-quality (1.1×105) factor wavelength filters. These demonstrations on the 193nm immersion lithography show superior performance both in terms of dimensional uniformity and device functionality compared to 248nm- or standard 193nmbased patterning in high-volume manufacture platform. Furthermore, using the wafer and patterning technology similar to advanced CMOS technology brings silicon photonics closer toward an integrated optical interconnect.

Improving defectivity for III-V CMP processes for <10 nm technology nodes

III-V high mobility channel materials are being considered for advanced devices beyond the 10 nm technology node. For pMOS devices, Ge and SiGe have already been shown to be viable candidates [1,2] while for nMOS devices our focus lies on III-V materials such as InP and InGaAs. For the integration of III-V channel materials, several approaches are being explored: the aspect ratio trapping (ART) method and hetero-epitaxy of III-V compound semiconductors on blanket Si using strain-relaxed buffer layers. This paper focuses on reducing the defectivity of the III-V layers during CMP steps needed for either approach. We show that the use of an improved pad/slurry combination can significantly reduce the CMP-induced damage to the InP fins in the ART approach and can achieve a post-CMP roughness r.m.s. of InGaAs SRB layers of ~0.7 nm.

CMP on SiGe materials — Linking chemical and physical properties to design low defect and selective slurries

Germanium as a high electron mobility material (HEMM) is considered to replace silicon in FET devices. However, since a lot of technical challenges for pure germanium still need to be overcome, Silicon-Germanium alloys (SiGe) devices combine properties of Silicon and Germanium almost linear depending on their composition and are easier to integrate. For p-MOS integration schemes, SiGe has shown to be a promising candidate [1]. Furthermore, Si1-xGex materials are used as strain relaxed buffer for Ge p-MOS devices. This paper shows on the one hand SiGe stochiometry dependent properties which are important during a CMP process e.g. etching rates and on the other hand demonstrates the latest developments of CMP slurries and their performance for such alloys. We show that slurries containing germanium enhancers and Poly-Si suppressors showed improved defect performance and excellent selectivities towards different substrates as eHarp and Poly-Si.

Dummy design characterization for STI CMP with fixed abrasive

The Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) process has an essential role in the STI module for the fabrication of the Complementary Metal Oxide Semiconductor (CMOS) transistors. Since the 0.13 μm technology node a direct STI CMP approach is used, where an oxide film is polished to remove the topography after trench fill and to clear the active regions stopping on a silicon nitride layer. One of the approaches for direct STI CMP uses a Fixed Abrasive (FA) web, which provides excellent planarity. Dummy structures are implemented in the device manufacturing layouts in order to overcome the effect of the different patterned densities and feature sizes. The design of the dummy structures plays a critical role for the CMP performance. In this work, a detailed characterization of the impact of the dummy design on the STI CMP performance using FA has been performed. Based on it, CMP optimized dummy designs have been found. The optimum dummy designs are vertical lines with higher patterned density (PD ~> 30 %) and smaller spacing in y (<; 1 μm) as well as segmented squares with bigger size (x = 5 μm, y = 5 μm, s = 1 μm), higher PD (-> 23 %) and smaller width and spacing of the lines.

In Depth Analysis of 3D NAND Enablers in Gate Stack Integration and Demonstration in 3D Devices

An in-depth analysis of gate stack enhancements that enable multi-Gb 3D NAND products is performed. Alternative charge trapping layer, enhanced tunnel oxide based on the VariOT concept and metal gate with Al2O3 high-k liner have been proposed and evaluated. The most promising solutions were successfully integrated in 3D devices. Integration challenges of the replacement gate approach, required to have metal gate in 3D NAND, are also analyzed and discussed in detail.