Gyoung-Ho Buh

Interface states as an active component for 20 nm gate-length planar MOSFET with electrostatic channel extension (ESCE)

Electrostatic channel extension (ESCE) MOSFET, a transistor with static inversion layer formed by interface fixed charge is fabricated in planar bulk structure down to 20 nm gate-length. The 24 nm gate-length ESCE transistor with current 80 nm gate-length SRAM technology shows the excellent drive currents of 1.0 mA/mum with IOFF of 93 nA/mum at VDS = 1 V. Moreover, the ESCE transistor with the gate oxide thickness of 10 Aring shows effectively suppressed gate-oxide leakage, very low GIDL, high breakdown voltage (> 6 V), immunity from CD variance, and robust reliability. The ESCE scheme is very promising to overcome the scale-down limit of planar transistor beyond 20 nm with ultra-low cost

Improved Cell Performance for sub-50 nm DRAM with Manufacturable Bulk FinFET Structure

FinFET, the milestone for sub-50 nm DRAM cell transistor has been successfully demonstrated by a unique fabricating method with novel concept. We obtained a core solution of front-end-of-line process and structure, focusing on short channel behavior, off-state leakage, and saturation current. We have developed the scheme that is able to suppress off-state leakage current below 1 fA/cell with p+ poly-Si gate. We have also examined mobility and parasitic engineering techniques to maximize the cell performance (DeltaIon > 48 %). In conclusion, we propose the effective guideline for highly manufacturable FinFET for DRAM application at the sub-50 nm node.

Issues of Ultrashallow Junction for Sub-50 nm Gate Length Transistors: Metrology, Dopant Loss, and Novel Electrostatic Junction

Issues of ultrashallow junctions (USJ) for sub-50 nm gate-length transistors are discussed. To measure the actual current drivability of source/drain extension (SDE), we developed SDE sheet resistance test structure (SSTS) which simulates the actual geometry and thermal condition of dopant underneath sidewall spacer. By using low energy electron induced X-ray emission spectrometry (LEXES) and other conventional techniques such as four point probe (FPP) and secondary ion mass spectrometry (SIMS), we quantified SDE dopant loss during the CMOS process and found that the wet-etching removal and outdiffusion are the most significant causes for dopant loss in n-SDE and p-SDE, respectively. Novel junction structures with electrostatic channel extension (ESCE) MOSFET for sub-20 nm gate-length transistor are presented as well

Electrical Characteristics of Ultrashallow p + ∕ n Junction Formed by BF3 Plasma Doping and Two-Step Annealing Process

We have investigated ultrashallow p + /n junctions formed by BF 3 plasma doping. Conventional one-step annealing processes such as rapid thermal annealing or excimer laser annealing (ELA) are not effective methods for high activation of boron. Furthermore, it is known that fluorine can retard dopant activation. In order to reduce fluorine concentration, we propose additional preannealing at 600°C for 10 min followed by ELA. This process dramatically improved the boron activation ratio, while maintaining the same junction depth. The improvement of dopant activation is attributed to significant out-diffusion of fluorine which in turn enhances activation of boron during ELA.

Ultrashallow p+/n junction prepared by low energy BF3 plasma doping and KrF excimer laser annealing

We have investigated the activation and deactivation of the 1 kV BE 3 plasma doping (PLAD) with excimer laser annealing (ELA). Half of the dopants were activated by ELA, and the deactivation was dramatically increased after the postannealing. We have confirmed that 1 kV BE 3 PLAD did not form an amorphous layer at the substrate using X-ray transmission electron microscopy (X-TEM) and that boron and fluorine segregated after annealing using secondary ion mass spectroscopy profiles and plane-view TEM. Based on the results, we proved that fluorine can suppress boron diffusion, although it retards the activation and increases the deactivation of BE 3 PLAD with ELA.