Hans-Olof Vickes

90 nm CMOS MMIC amplifier

Small signal amplifiers at 20 and 40 GHz, based on a 90 nm CMOS process are demonstrated. A gain of 5.8 dB at 20 GHz for single stage has been obtained with a 1 dB compression point at 1 dBm. The corresponding figures for the 40 GHz amplifiers are 6 dB and -5.75 dBm. Noise figure for the 20 GHz amplifier is 6.4 dB. Both single gate access and double gate access transistors have been used in the design. DC power consumption of the 20 GHz single stage amplifier was found to be 10 mW whereas for the 40 GHz double stage amplifier it is approximately 19 mW. Total circuit area is 0.7/spl times/0.8 mm/sup 2/ for the single stage and 1/spl times/0.7 mm/sup 2/ for the 40 GHz double stage amplifier.

A General Statistical Equivalent-Circuit-Based De-Embedding Procedure for High-Frequency Measurements

A general equivalent-circuit-based method for the de-embedding of scattering parameters is presented. An equivalent circuit representation is used to model the embedding package. The parameters in the models are estimated with a statistical method using measured data from all de-embedding standards jointly together. Hence, it is possible to assess parameter estimates and their variance and covariance due to measurement uncertainties. A general de-embedding equation, which is valid for any five-port with a defined nodal admittance matrix, is derived and used in the subsequent de-embedding of measured device data. Different equivalent circuit models for the embedding network are then studied, and tradeoffs between model complexity and uncertainty are evaluated. Furthermore, the influence of varying number and combinations of de-embedding standards on the parameter estimates is investigated. The method is verified, using both measured and synthetic data, and compared against previously published work. It is found to be more general while keeping or improving accuracy.

Determination of intrinsic FET parameters using circuit partitioning approach

A technique useful in extracting intrinsic parameters for a compound semiconductor FET is presented. The technique makes use of a method provided by G. Dambrine et al. (1988). A modified active circuit that accounts for charge accumulation in the conducting channel is presented. The model has the further advantage of using control voltage modeling in agreement with the Curtice convention for large-signal analysis. The equations are presented for each active element as a function of the intrinsic y parameters. Measurements verify the parameter extraction technique with the circuit topology used and show good results. >

The Matrix Balun—A Transistor-Based Module for Broadband Applications

In this paper the analysis and design of a new active balun with very broadband performance, the matrix balun, are reported. Measured results show a common mode rejection ratio, CMRR, larger than 15 dB between 4 and 42 GHz while exhibiting 2 dB single-ended gain with a ripple of 1 dB. The balun was realized in a 0.15 mum GaAs mHEMT process. It occupies a chip area of 0.63 mm2 and consumes a dc power of 20 mW. The same matrix balun circuit may also be biased for amplification and used as a matrix amplifier. The circuit then exhibits 10.5 dB gain up to 63 GHz with 1 dB ripple above 5.5 GHz and a power consumption of 67 mW.

CMOS MMICs for microwave and millimeter wave applications

Recent results on MMIC based on a 90-nm CMOS process are presented. Linear and nonlinear models were developed for the transistors based on S-parameters, noise parameters, and power spectrum measurements. Based on EM-simulations, models for multilayer capacitances, MIM-capacitances, various transmission lines etc were also developed. Amplifiers, frequency mixers, and frequency multipliers were then designed, fabricated and characterized. Amplifiers with a gain of 6 and 3.5 dB per stage at 20 and 40 GHz respectively, were demonstrated as well as frequency multipliers from 20 to 40 GHz with 15.8 dB conversion loss, and 30 to 60 GHz multipliers with 15.3 dB conversion loss. Resistive mixers at 20, 40, and 60 GHz were also demonstrated with promising results.

CMOS large signal model for CAD

A compact large-signal model for high frequency CMOS transistors is proposed and experimentally evaluated with DC, S-parameter power spectrum measurements and load pull measurements. Very good correspondences between measurements on 100 nm CMOS FETs (f/sub T/ = 140 GHz, f/sub max/ =100 GHz) and simulations were achieved. Due to the low number of model parameters and the careful selection of model equations, the model exhibits excellent convergence behavior, a property important for successful nonlinear circuit simulation of RF circuits.

90-nm CMOS for microwave power applications

We report, for the first time, the experimental evaluation of a very short channel 90-nm CMOS transistor under RF over-voltage conditions. At 9 GHz and 1.5 V supply a 40 /spl mu/m gate width device is able to deliver 370 mW/mm output power with a PAE of 42% and a transducer power gain of 15 dB. Measurement results at 3 and 6 GHz is also presented. The transistor does not show any degradation in either dc or RF performance after prolonged operation at 1 and 6 dB compression. Simulation show, that the peak voltage, V/sub ds/ at this condition is 3.0 V, while the maximum allowed dc supply voltage is limited by the design rules to 1.2 V. We show for the first time that nanometer-scale CMOS can be used for microwave power applications with severe RF over-voltage conditions without any observable degradation.

A new programmable load for noise parameter determination

A new computer-controlled programmable load is presented. The load consists of a cascade of p-i-n diodes bonded to each other. The capacitance of the reverse-biased p-i-n diode, together with the interconnecting bonding wires, forms an artificial transmission line. A complete phase coverage in the Smith chart is obtained by forward biasing any diode pair, using only two current generators and two multiplexers. The amplitude coverage will depend on the diode spacing. The load may be set to any reflection coefficient within its coverage area. Synthesis formulas for the determination of the current driver settings have been derived. A calibration procedure determining the unknown synthesis parameters from input port measurements only is presented. Only the p-i-n diode parameters are characterized separately. The programmable load has been built and tested. Measurements verify the principle and show good agreement with computer simulations. The load has been developed for noise parameter determination. Other applications for variable impedance measurements are circuit or device optimization of gain output power performance. >

CMOS devices and circuits for microwave and millimeter wave applications

Recent results on characterization, modelling and circuit design based on 90/130 nm CMOS is presented in this paper. Amplifiers, frequency multipliers, and mixers were realized for frequencies up to 60 GHz. Circuit results based on two different transmission line approaches are reported. Load-pull characterization of transistors at 9 GHz and 23 GHz are also reported with 250mW/mm and 150 mW/mm output power for a 90 nm and 130 nm CMOS technology respectively. Initial studies of FINFETs promise feasibility of analogue circuits up to millimetre wave frequencies.

The combiner matrix balun, a transistor based differential to single-ended module for broadband applications

In this paper a new active combing balun, i.e. differential input to single-ended output, with broadband performance, the combiner matrix balun, is presented. Measured results show an amplitude and phase difference of less than 1 dB and 20 degrees from 5 to 40 GHz together with a gain of 2 dB with less than 1 dB ripple. The topology is easily scaled up in frequency and gain and also technology independent making it an interesting choice for future broadband differential applications.