Martin Manley

Transistor off-state leakage current induced by TiSi 2 pre-amorphizing implant in a 0.20 μm CMOS process

We report on an anomalous off-state leakage current found in NMOS devices fabricated with a pre-amorphizing (PA) implant before titanium silicide formation. We present data which indicates that the leakage current is caused by channeling of the arsenic PA implant through the polysilicon gate. An angled PA implant is shown to prevent the channeling and allow the fabrication of well-behaved devices with low resistance titanium silicide.

Systematic methodology for optimizing the tradeoff of polysilicon depletion versus boron penetration in sub-0.18-μm surface-channel PMOS devices

Control of boron penetration in surface-channel PMOS devices is critical in order to ensure tight threshold voltage (Vt) distribution. Previous work has focused on studying relatively gross boron-penetration effects, which give rise to large shifts in Vt. In practice, low-voltage CMOS technologies are sensitive to small degradation in PMOS Vt scatter due to the onset of boron penetration. Moreover, the use of rapid thermal annealing can give rise to difficult trade-offs between poly depletion and boron penetration. As both of these effects can influence the PMOS Vt we propose a sensitive, systematic, methodology to distinguish between depletion and penetration effects and illustrate its application in a number of advanced CMOS processes, with oxide thickness ranging from 30-50 angstrom.

Optimized shallow trench isolation for sub-0.18-μm ASIC technologies

An integrated shallow trench isolation process utilizing HDP (High Density Plasma) oxide and a highly manufacturable corner oxidation is described. The choice of trench corner oxidation temperature is shown to be critical in reducing silicon stress, and hence junction leakage, to the levels required by multi-million gate designs. This STI process is shown to be extremely robust and manufacturable. Optimal design of the trench depth and well profiles is shown to provide well-edge isolation adequate for sub-0.18 micrometer technologies.

Plasma-induced oxide contamination in a 0.35-um CMOS process

Plasma contamination in a 0.35 micrometer triple-level metal CMOS process was investigated in response to anomalous dc parametric test data. Electrical PMOS transistor performance and both physical and electrical gate oxide thickness were significantly degraded upon exposure of a sacrificial oxide to a plasma ash following a masked, P-channel threshold adjust ion implant. The contamination was isolated to a specific asher, found to be radial in nature across a wafer, and consistently worse in one of the two chambers used during the ash process. The contamination dramatically reduced the wet etch rate of the sacrificial oxide, leading to incomplete removal prior to gate oxide growth. Increasing the wet strip time of the sacrificial oxide improved the ability to remove this contaminated film, but was limited by minimal field oxide thickness requirements to avoid field inversion. Transferring the ash process to an alternative, low-damage, down-stream asher eliminated the plasma contamination.