Heung-soo Park

A Highly Reliable Cu Interconnect Technology for Memory Device

This paper describes the development of Cu interconnect technology for memory devices. A highly reliable sub 50 nm Cu interconnect lines were successfully fabricated by using optimized iPVD barrier/seed and electroplating process. The resistivity of Cu lines was reviewed with that of Al for extendibility of Cu. The Cu TDDB lifetime in user conditions was investigated to confirm the reliability of Cu process integration. It can be predicted that Cu metallization can satisfy the requirements of sub 50 nm trench pattern, which are lower resistance than Al and good reliabilities.

Plasma charge-induced corrosion of tungsten-plug vias in CMOS devices

Plasma charge-induced corrosion of tungsten plug vias, where part of the via surface is exposed to the chemical solution after metal-2 etch by photolithographic misalignment with upper metal lines, was investigated. Some electrochemical tests and plasma damage monitoring were done to study the corrosion mechanism. The configuration of circuits was also investigated to understand the pattern dependency of the plasma damage and the corrosion. It is believed that the positive charges on the metal lines and P/sup +/ active region of the PMOS, developed during dry etching and ashing, are enhancing the corrosion of tungsten during stripping. The plasma-less O/sub 3/ asher applied to the ashing process reduced the plasma damage and did not produce empty vias on the wafer.

Effect of Surface Iron on Photoconductivity Carrier Recombination Lifetime of p‐Type Silicon

Vacuum-evaporated iron caused a severe degradation in minority carrier lifetime irrespective of the cleans used indicating lifetime degradation is related to initial iron concentration, not merely to final iron concentration after cleaning. It was found to take at least three separate steps (within the RCA-based cleans) to effectively remove iron from hydrofluoric acid solution-last surfaces. It also was found that precipitates caused by iron contamination were formed underneath thermally grown silicon oxide at 920°C. The defects are believed to be iron silicides formed during the oxidation of iron-contaminated silicon.

A NEW POST-TREATMENT FOR CHEMICAL-MECHANICAL POLISHING PROCESS OF VERY LARGE-SCALE INTEGRATED CIRCUIT TUNGSTEN VIAS

A method of cleaning silicon substrates after chemical-mechanical polishing (CMP) for the planarization of tungsten-plug patterned silicon wafers is discussed. A phosphoric acid solution with fluoroboric acid (PFM) is used for the post treatment process to replace the conventional scrubbing process. The optimum chemical composition for the new solution is found to be the mixing ratio of 1:50 (fluoroboric acid:phosphoric acid in volume) at a phosphoric acid concentration of 40 vol%. Its oxide selectivity over metals and particle removing power are good enough for the cleanup process after CMP. The contact resistance of vias treated by the PFM solution exhibits a good distribution compared to that of vias treated by conventional scrubbing. In conclusion, the PFM solution shows promising results as a post-treatment to W CMP of via contact formation.