Hidemitsu Mori

A 1-Gb DRAM for file applications

A number of large capacity DRAMs have been developed recently for file applications because data storage devices play an important role in high-speed communication and graphic systems. Such file memories must have low power dissipation, high data transfer rate and low cost. A low chip-yield problem is reported to occur in the manufacture of large capacity DRAMs. To address both device requirements and yield limitations, new circuit technologies have been developed for 1 Gb DRAMs. By implementing a time-shared offset cancel sensing scheme and adopting a diagonal bit-line (DBL) cell, the chip size is reduced to 70% of that of a conventional DRAM. A defective word-line Hi-Z standby scheme and a flexible multi-macro architecture produces about twice the yield as that resulting from conventional architecture. 32 b I/Os with a pipeline circuit technique realizes a 400 MB/s data transfer rate. A 1 Gb DRAM with these features uses 0.25 /spl mu/m CMOS.

A 128 kb FeRAM macro for a contact/contactless smart card microcontroller

For contact/contactless smart-card applications, a ferroelectric RAM (FeRAM) macro must operate with supply voltages ranging from 2.7 V to 5.5 V, as standardized by ISO, and have endurance of more than 10/sup 8/ write/read cycles and memory size flexible from 32 kb to 128 kb. In addition, for contactless smart card applications, low current consumption is essential. This macro meets these requirements using: (1) 3-metal process capacitor-on-metal/via-stacked-plug (CMVP) memory cell; (2) voltage regulation architecture; (3) main/sub bit line and word line structure; and (4) dynamic-type offset sense amplifier.

A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers

For contact/contactless smart-card applications, a ferroelectric RAM (FeRAM) macro must operate with supply voltages ranging from 2.7 V to 5.5 V, as standardized by ISO, and have endurance of more than 10/sup 8/ write/read cycles and memory size flexible from 32 kb to 128 kb. In addition, for contactless smart card applications, low current consumption is essential. This macro meets these requirements using: (1) 3-metal process capacitor-on-metal/via-stacked-plug (CMVP) memory cell; (2) voltage regulation architecture; (3) main/sub bit line and word line structure; and (4) dynamic-type offset sense amplifier.

Separation of intrinsic and parasitic MOSFET parameters using a multiple built-in Kelvin test structure

A new MOSFET test structure built in multiple Kelvin patterns is used to evaluate scaled-down MOSFET characteristics through separation of intrinsic and parasitic parameters. Transistor characteristics and contact resistance of individual MOSFETs are simultaneously measured to clarify the direct correlation between fluctuation of MOSFET characteristics and that of parasitic contact resistance. MOSFET performance without parasitic interconnect resistance can be also measured to define intrinsic current drivability in a MOSFET fully scaled-down to less than sub-half-micrometers dimensions.

A high-endurance 96-Kbit FeRAM embedded in a smart card LSI using Ir/IrO2/PZT(MOCVD)/Ir ferroelectric capacitors

We have developed a logic-embedded 96-Kbit FeRAM macro that has low-voltage operation and high-endurance features for smart card applications. The smart card LSI was fabricated using a 0.35 /spl mu/m-standard CMOS process with 3-level metallization and CMVP ferroelectric capacitors. The operation of the chip was confirmed at voltages from 2.7 to 5.5 V with 2.5 MHz clock cycle. By using Ir-based top and bottom electrodes, the fatigue endurance of the FeRAM was improved, which was confimed in burn-in tests. No failed bits were observed at accelerated conditions with 5.5 V and 150/spl deg/C after 10/sup 8/ fatigue cycles.