Hidenori Okuni

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication

A fully-integrated single-chip CMOS transceiver with MAC and PHY for 60GHz proximity wireless communication is presented. A 60GHz wireless communication single-chip transceiver has not yet been reported due to large power consumption issues. However, by limiting the application to high-throughput proximity transmission, thermal issues arising in a single-chip have been overcome. A 2GHz broadband OFDM single-chip transceiver suffers from SNR degradation due to the reference clock (REFCLK) and baseband clock (BBCLK) spurs in RF/analog circuits. Low frequency spurs in the clock generator (CLKPLL) due to the mixing of the ADC/DAC sampling clock (SCLK) and other clocks such as REFCLK and BBCLK have been eliminated by careful frequency planning of those clocks. In addition to that, spur suppression in digital baseband and noise-tolerant RF/analog circuit designs are employed. The spurs have been successfully suppressed to less than -35dBc. The chip achieves a PHY data-rate of 2.35Gb/s and MAC throughput of 2.0Gb/s at a distance of 4cm. Power consumption is scalable to the throughput by the introduction of fast Sleep and Awake modes. The average power consumption at a throughput of 0.2Gb/s is reduced to 36% of that at 2.0Gb/s.

Balanced 3-phase analog signal processing for radio communications

Radio communication systems often use two analog signals as real and imaginary parts of a complex number; the two signals are usually called I and Q signals. The analog signal on an integrated circuit is usually a differential signal which is the voltage difference between positive and negative nodes. Therefore, a complex number is expressed using 4-node voltages. If a single-ended signal system is used, I and Q signals are expressed with 3-node voltage, i.e., I-signal, Q-signal, and a ground node voltage. So the 4-node system has some redundancy. However, most radio terminals employ the 4-node system, because a single-ended signal system needs a low-impedance ground node, which is troublesome on an integrated circuit. In this paper, balanced 3-phase analog signal processing and circuits for the 3-phase system are proposed. The proposed circuits are simply expanded differential circuits and expected to have small chip area because of the lower redundancy in processing a complex number. The smaller chip area means lower manufacturing cost. The proposed system is expected to reduce the cost of a radio interface

A Direct Conversion Receiver with Fast-Settling DC Offset Canceller

In direct conversion receivers, which down-convert RF signal to baseband directly, DC offset in the baseband signal significantly degrades receiver performance and thus the DC offset cancellation is one of the most important issues regarding the achievement of high receiving performance. This paper proposes a fast-settling DC offset canceller that eliminates DC offset using stored DC data estimated in advance so as to cancel residual DC offset by a feedback loop. Experimental results and computer simulation results show that the DC offset canceller can eliminate a DC offset within 5 [musec], although it does not remove the desired signal component so as not to degrade BER (bit error rate) performance, because cut-off frequency in the HPF (high-pass filter) characteristic due to DC offset cancellation can remain low.

26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS

Various Ultra-Low-Power (ULP) RX architectures [1-4] for Bluetooth™ Low Energy (BLE) have been developed for minimizing the RX power consumption. A PLL-based RX architecture [1] is very attractive to improve the energy efficiency. While the single-channel configuration without multi-bit ADC realizes under 3mW power consumption and over -90dBm sensitivity, the 2nd and 3rd Adjacent Channel Interference Rejections (ACRs) do not meet the BLE requirements. Although the ACR can be improved by inserting high-order LPFs into the regeneration loop, it critically degrades the closed-loop stability. The Sliding IF (SIF) architecture is an alternative approach to overcome the ACR issue with high-energy efficiency. The reported receivers in [2,3] succeed in achieving over 20dB ACR, however, the SIF still has a problem of low out-of-band blocker tolerance because of unwanted signal at the image frequency. An off/on chip bandpass filter inserted at the front of the LNA can reject the image signal, which incurs a signal loss and degrades the energy efficiency of the RX. This paper presents a new PLL-based RX with hybrid loop that achieves over 20dB 2nd/3rd ACR without any external RF filters. The proposed RX employs two key features: (1) the high-interference-tolerance hybrid-loop structure based on an ADPLL, and (2) a novel single-channel receiving method, which enables the conversion of the constellation from FSK to a differential BPSK (DBPSK) signal.

A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS

This paper presents a low-power hybrid-loop receiver (RX) with high-interference tolerance for Bluetooth low energy (BLE). The hybrid-loop structure based on an all-digital phase-locked loop enables the RX to both enhance the interference tolerance and digitize the frequency-modulated signal without an ADC. A novel single channel receiving method, which enables the conversion of the constellation from frequency shift keying to differential binary phase shift keying signal, is adopted to eliminate the Q-channel signal processing to reduce the power consumption. The prototype RX fabricated in a 65 nm CMOS technology consumes only 5.5 mW and fulfills the BLE requirements of the adjacent channel rejection and out-of-band blocker tolerance without exception. The sensitivity level is -90 dBm.

A low-power high-Q matching LNA with small-size matching calibration circuit for low power receiver

To reduce power consumption of the receiver, high-Q matching low noise amplifier (LNA) can be used to reduce the power consumption of the LNA. In this work, we propose a small-size high-accuracy calibration circuit for the high-Q matching LNA. The proposed circuit is constructed by two power detectors and a comparator, which has overall area of 75×35μm2 in a 65 nm CMOS process. By comparing the amplitudes of differential input signals, the optimum setting of the matching circuit is determined. The proposed method can achieve high accuracy matching calibration without the knowledge of the input power. A LNA with proposed calibration circuit is fabricated by 65 nm CMOS process. The evaluation result proves the proposed calibration method effectiveness.

19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC

Several research studies have considered replacing traditional analog PLLs with an all-digital PLL (ADPLL). In such studies, a key topic relates to the resolution and linearity of the TDC. Power-hungry techniques, such as a Vernier delay line (VDL) and a time amplifier (TA) [1,2], have been proposed to improve time resolution. Recently, a digital-to-time converter (DTC) has been employed to enable power reductions of the VDL and TA-based TDCs by minimizing the number of VDLs and TAs [3,4]. However, the nonlinearity of the DTC remains a problem, since it is much larger than the time resolution of the TDCs and becomes a significant source of fractional spur in the ADPLL. In [3], the effect of the nonlinearity is decreased by utilizing a dithering technique at the expense of a long calibration time (> 100ms). The DTC requires inherently more calibration effort for full-scale-delay detection and normalization, since the difference between the full-scale delay and the DCO period also increases the fractional spur significantly. On the other hand, time-to-amplitude-conversion-based TDCs may be another candidate for a high-resolution low-power TDC [5]. However, issues surrounding the nonlinearity of the charge pump (CP) and the full-scale-delay detection limit their utility.

A wide bandwidth analog front-end circuit for 60-GHz wireless communication receiver

This paper presents an analog front-end circuit for a 60-GHz wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224 mW Power consumption.