Tuan Thanh Ta

26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS

Various Ultra-Low-Power (ULP) RX architectures [1-4] for Bluetooth™ Low Energy (BLE) have been developed for minimizing the RX power consumption. A PLL-based RX architecture [1] is very attractive to improve the energy efficiency. While the single-channel configuration without multi-bit ADC realizes under 3mW power consumption and over -90dBm sensitivity, the 2nd and 3rd Adjacent Channel Interference Rejections (ACRs) do not meet the BLE requirements. Although the ACR can be improved by inserting high-order LPFs into the regeneration loop, it critically degrades the closed-loop stability. The Sliding IF (SIF) architecture is an alternative approach to overcome the ACR issue with high-energy efficiency. The reported receivers in [2,3] succeed in achieving over 20dB ACR, however, the SIF still has a problem of low out-of-band blocker tolerance because of unwanted signal at the image frequency. An off/on chip bandpass filter inserted at the front of the LNA can reject the image signal, which incurs a signal loss and degrades the energy efficiency of the RX. This paper presents a new PLL-based RX with hybrid loop that achieves over 20dB 2nd/3rd ACR without any external RF filters. The proposed RX employs two key features: (1) the high-interference-tolerance hybrid-loop structure based on an ADPLL, and (2) a novel single-channel receiving method, which enables the conversion of the constellation from FSK to a differential BPSK (DBPSK) signal.

A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS

This paper presents a low-power hybrid-loop receiver (RX) with high-interference tolerance for Bluetooth low energy (BLE). The hybrid-loop structure based on an all-digital phase-locked loop enables the RX to both enhance the interference tolerance and digitize the frequency-modulated signal without an ADC. A novel single channel receiving method, which enables the conversion of the constellation from frequency shift keying to differential binary phase shift keying signal, is adopted to eliminate the Q-channel signal processing to reduce the power consumption. The prototype RX fabricated in a 65 nm CMOS technology consumes only 5.5 mW and fulfills the BLE requirements of the adjacent channel rejection and out-of-band blocker tolerance without exception. The sensitivity level is -90 dBm.

A 3.2 mA-RX 3.5 mA-TX fully integrated SoC for Bluetooth Low Energy

A fully-integrated system-on-chip (SoC) for Bluetooth Low Energy (BLE) with 3.2 mA RX and 3.5 mA TX current consumption is presented. To achieve both low current consumption and high performance, the SoC employs a sliding-IF architecture that avoids out-of-band-blocking signals, a power management unit with improved efficiency, and techniques to reduce current in core circuits. The SoC achieves RX sensitivity of −93 dBm and maximum output power of 0 dBm. The SoC is in compliance with version 4.2 of the Bluetooth specifications and with the radio regulations of the FCC, ETSI, and ARIB. The SoC achieves the worlds lowest current consumption for both RX and TX modes in the published product-level SoCs.

A low-power high-Q matching LNA with small-size matching calibration circuit for low power receiver

To reduce power consumption of the receiver, high-Q matching low noise amplifier (LNA) can be used to reduce the power consumption of the LNA. In this work, we propose a small-size high-accuracy calibration circuit for the high-Q matching LNA. The proposed circuit is constructed by two power detectors and a comparator, which has overall area of 75×35μm2 in a 65 nm CMOS process. By comparing the amplitudes of differential input signals, the optimum setting of the matching circuit is determined. The proposed method can achieve high accuracy matching calibration without the knowledge of the input power. A LNA with proposed calibration circuit is fabricated by 65 nm CMOS process. The evaluation result proves the proposed calibration method effectiveness.

19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC

Several research studies have considered replacing traditional analog PLLs with an all-digital PLL (ADPLL). In such studies, a key topic relates to the resolution and linearity of the TDC. Power-hungry techniques, such as a Vernier delay line (VDL) and a time amplifier (TA) [1,2], have been proposed to improve time resolution. Recently, a digital-to-time converter (DTC) has been employed to enable power reductions of the VDL and TA-based TDCs by minimizing the number of VDLs and TAs [3,4]. However, the nonlinearity of the DTC remains a problem, since it is much larger than the time resolution of the TDCs and becomes a significant source of fractional spur in the ADPLL. In [3], the effect of the nonlinearity is decreased by utilizing a dithering technique at the expense of a long calibration time (> 100ms). The DTC requires inherently more calibration effort for full-scale-delay detection and normalization, since the difference between the full-scale delay and the DCO period also increases the fractional spur significantly. On the other hand, time-to-amplitude-conversion-based TDCs may be another candidate for a high-resolution low-power TDC [5]. However, issues surrounding the nonlinearity of the charge pump (CP) and the full-scale-delay detection limit their utility.