Yoshiharu Tosaka

Scaling theory for double-gate SOI MOSFET's

A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator. >

Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM's

Although it has been shown that cosmic ray neutrons play an important role in soft error (SE) phenomena, some important issues remain to be clarified in neutron-induced SE phenomena. This letter reports the geometric effect of multiple-bit SEs induced by neutrons. Multiple-bit SEs in 16 Mb DRAMs are investigated and their geometric effects on high reliability systems are discussed.

Simulation technologies for cosmic ray neutron-induced soft errors: Models and simulation systems

The authors review two types of simulators for the analysis of cosmic ray neutron-induced soft errors (SEs). One of them is the neutron-induced soft error simulator (NISES). A recently proposed nuclear reaction theory forms the foundation for the nuclear reaction database used in NISES. The other simulator, the simplified simulator MBGR, is based on a modified version of the burst generation rate (BGR) model. Both simulators accurately simulate neutron-induced SE rates (SERs). MBGR actually provides an easier and quicker estimation of neutron-induced SERs than NISES. On the other hand, NISES covers more applications: it simulates neutron-induced charge collection, multiple-bit SE, and /spl alpha/-induced SE analysis.

Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's

We derived a simple formula for the subthreshold swing S in double-gate (DG) SOI MOSFETs. Our formula, which depends only on a scaling device parameter, matches the device simulation results. From these results, our equations are simple and give a scaling rule for DG-SOI MOSFETs.<<ETX>>

Measurement and analysis of neutron-induced soft errors in sub-half-micron CMOS circuits

Neutron-induced soft error rates (SERs) of subhalf-micron CMOS SRAM and Latch circuits were studied both experimentally and analytically to investigate cosmic ray neutron-induced soft errors (SEs). Because the neutron beam used in the measurement has an energy spectrum similar to that of sea-level atmospheric neutrons, our SER data corresponds to those induced by cosmic ray neutrons. The /spl alpha/-particle induced SERs were also measured for comparison with the neutron-induced SERs. Neutron-induced SEs occurred in both circuits. On the other hand, /spl alpha/-induced SEs occurred in SRAM, but not in the Latch circuits. The measured SERs agreed with simulated results. We discussed the significance of how cosmic ray neutrons affects CMOS circuits at ground level.

Comprehensive study of soft errors in advanced CMOS circuits with 90/130 nm technology

Characteristics of soft errors (SEs) in 90/130 nm CMOS circuits were comprehensively investigated by high energy neutron- and alpha-accelerated tests. Process dependence on SEs in latch circuits due to neutrons and alpha-ray were investigated. Error patterns in multiple-bit SEs in SRAMs and their impacts on ECC design were also discussed.

Analytical threshold voltage model for short channel double-gate SOI MOSFETs

Solving a two-dimensional (2-D) Poisson equation and assuming the minimum potential determines the threshold voltage, V/sub th/, we derived a model for V/sub th/ of short channel double-gate SOI MOSFETs, and verified its validity by comparing with numerical data. We evaluated the threshold voltage lowering, /spl Delta/V/sub th/, and subthreshold swing (S-swing) degradation with decreasing gate length L/sub G/, and showed that we can design a 0.05-/spl mu/m-L/sub G/ device with /spl Delta/V/sub th/ of less than 50 mV and an S-swing of less than 70 mV/decade if 10-nm-thick SOI is available.

Simple method for estimating neutron-induced soft error rates based on modified BGR model

Recently the importance of cosmic ray neutron-induced soft errors has been recognized. We propose a simple model to estimate the neutron-induced soft error rates (SERs), which is a modified version of the burst generation rate (BGR) model. Our model can be used to easily and quickly estimate neutron-induced soft error rates and provides a useful guideline for device and circuit engineers to estimate neutron-induced soft errors (SEs),.

SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET

We have developed a robust latch for achieving high reliability in LSI. The latch can attenuate multi-node single-event-upset (MNSEU) and single event transient on local-clock (SETLC). The robust latch has Dual-clock-buffers (DCB) and Double-height-cell (DHC) technologies. Results on neutron acceleration experiments show that DHC can dramatically attenuate MNSEU and DCB can protect almost SETLC of the latch. In addition, we investigate optimum design in well structure.

Impact of cosmic ray neutron induced soft errors on advanced submicron CMOS circuits

We numerically studied the neutron effects on submicron CMOS SRAM and LATCH circuits using a developed simulator which agrees well with the experimental charge collection measurements. We showed that the neutron effects have influence on SEs in advanced integrated circuits, especially for LATCH. If the Pb-Sn solder or other materials with high /spl alpha/-particle emission rates are not included, the neutrons are main SE components in advanced integrated circuits.