Naohiro Matsukawa

A new technique for measuring threshold voltage distribution in flash EEPROM devices

A new, simple test circuit for evaluating the reliability of flash EEPROM devices is described. It measures threshold voltage (V/sub th/) distributions of a large number of cell transistors with easy static operation similar to I-V curve measurement. Moreover, each cell transistor in a large array is selectable to measure static characteristics. This circuit makes it possible to measure the V/sub th/ distribution even in the negative region after erase operation for a NAND-type EEPROM.

Selective polysilicon oxidation technology for VLSI isolation

Field isolation technology is described for small geometry VLSIs in which selective polysilicon oxidation is essential. The technology, also known as SEPOX, offers resist pattern reproducibility in field oxide, while maintaining crystal perfection in the substrate. By a series of experiments, high oxide reliability resulting from a white ribbon-free nature, long lifetime from C-T measurement, and small leakage currents in a reverse biased p-n junction were obtained, as well as a small geometry structure. The feasibility of this technology for MOS LSIs were examined in a 3-µm rule memory chip, and a reasonable yield and reliability were obtained. The physical limitations of SEPOX were also considered and submicrometer capability was confirmed.

An EEPROM cell using a low barrier height tunnel oxide

A new simple method to fabricate a thin oxide with low barrier height is proposed. An oxide is grown on a heavily implanted silicon substrate with As or P in excess of 5 × 10¹⁴/cm². When the oxide was grown in H<inf>2</inf>O + Ar gas after Ar annealing, the barrier height of the oxide conduction band with respect to the silicon conduction band decreased to 1.8 eV, about one half of the ordinary value of 3.2 eV. This phenomenon was applied to an EEPROM cell, which showed superior WRITE/ERASE characteristics. A moderately implanted As (2.5 × 10¹⁵/ cm²) sample shows excellent WRITE/ERASE endurance, over 10⁶cycles with 2-V V<inf>th</inf>window, which could not realized by using an ordinary oxide.

A hot hole-induced low-level leakage current in thin silicon dioxide films

A new kind of stress-induced low-level leakage current (LLLC) in thin silicon dioxide is reported. It is observed after the stress of hot hole injection at the gate edge. Since voltage dependence of this new kind of LLLC is steeper than that of conventional FN stress-induced LLLC, each conduction mechanism may be different. This LLLC is reduced by both hot electron injection and UV irradiation. These reductions are never observed in FN stress-induced LLLC. The most promising mechanism is sequential tunneling via trapped holes.

Selective polysilicon oxidation technology for defect free isolation

A new isolation technology is described for small geometry MOS LSIs in which selective polysilicon oxidation is utilized. In the process, a polysilicon film is deposited on a oxide layer grown on a silicon substrate, first. Thick thermal oxide is then selectively formed by polysilicon oxidation with a masking Si3N4film without pad oxide. The unoxidized polysilicon is etched off by a reactive ion etching, and then the residual polysilicon under the overhung oxide is oxidized for providing desired field oxide edge configuration. A test device was fabricated by this technology and the birds beak length was reduced to 0.15 µm, typically, in the case of no pad oxide. The feasibility of this technology for MOS VLSIs was confirmed without any serious process induced defects.

A hot carrier induced low-level leakage current in thin silicon dioxide films

A new kind of stress induced low level leakage current (LLLC) in thin silicon dioxide is reported. It is observed after the stress of hot hole injection at the drain edge. Since the voltage dependence of this new kind of LLLC is steeper than that in the conventional FN stress-induced LLLC, each conduction mechanism may be different. This LLLC is reduced by both hot electron injection and UV irradiation. These reductions are never observed in the FN stress-induced LLLC. The most promising conduction mechanism is sequential tunneling via trapped holes.

Characteristics and reliability of the SEPROM cell

A new EPROM named SEPROM, based on a modified SEPOX process, is proposed and evaluated. The SEPROM offers a process compatibility to logic LSIs with higher packing density, since the area of the second gate oxide is equal to that of the first gate oxide. To improve the coupling capacitance ratio, which relates to write and read operations, a thin second gate oxide is required for the SEPROM cell at a risk of degradation in charge retention characteristics. A measured test device, however, shows sufficiently good characteristics both in programming and charge retention, due to the desirable structure of the cell. The SEPROM structure appears to be practical and promising for both EPROM and logic device applications.

Distributed-cycling Effects for Data Retention Characteristics of Flash Memories

The dependence of the distributed-cycling effects on data retention characteristics of flash memories with NAND type operation on the cycling temperature and interval was investigated. The slope of Vt shift curves in the logarithm of bake time changes with the cycling temperature regardless of the cycling interval. On the other hand, the time offset of Vt shift curves changes with the cycling interval regardless of the cycling number. These phenomena are qualitatively explained by the tunneling front model. Using these results, data retention time with a long cycling interval can be predicted from a very short time cycling test in low temperature. Introduction Recently, the distributed-cycling effect on data retention characteristics of NOR type flash memories was reported [1]. It assumes that Vt shifts logarithmically with bake time and the cycling rate, or the cycling interval, only affects to the x-intercept of the Vt shift curve in the logarithm of bake time, which is named a time offset in this paper. The same slope is also assumed independent of cycling conditions, the cycling temperature and interval, and slope changes are not considered in data analysis. It assumes the slope changes only by the cycling number. The tunneling front model (TFM) [2] is widely accepted to explain MOSFET’s Vt shift due to charge de-trapping from the gate oxide. According to the model, in case of uniform charge density, Vt shifts logarithmically with bake time and its slope is proportional to the trapped charge density. The gate oxides under different degraded conditions shows different slopes of Vt shift curves. We observed this phenomenon in the NAND flash memory cells with the different cycling temperatures even with the same cycling number. Fig.1 shows Vt shifts of cycled memory cells in the different temperatures with the same cycling interval of 2 minutes and cycling number of 3.6K. A high temperature cycling condition induce a steeper slope, which means a higher temperature cycling generates a higher charge density. This difference of the slopes is very important to decide the data retention lifetime. And this change is not expressed by single activation energy, since temperature acceleration changes with Vt shift value. This is one of the main subjects of this paper. Fig.1 also shows the cycling temperature much affects the horizontal positions, or the time offsets, of Vt shift curves. The time offset dependence on the cycling temperature and interval is another subject of this paper. Experimental Experiments were performed on a giga-bit class memory array with NAND type operation. One cycling and bake condition is applied to a part (2G cells unit) of large array. 3.6k cycling were performed in temperature ranging from 25C to 85C with the cycling interval ranging from 0.5 minutes to30 minutes. In order to investigate a cycling number effect, 1.2k cycling was also performed. Retention bake was performed at 85C. Vt shift was measured at the Vt distribution edge, which was defined by Vt of 10000 cell from the lowest Vt cell. For longer cycling interval conditions, so called final 10% method [1] was applied. Results and analysis A. Experimental results and tunneling front model (TFM) Fig.2 shows representative experimental results of Vt shift with the cycling intervals of 2 minutes and 30 minutes. Each pair of Vt shift curves, which composed of 1.2k cycling and 3.6k cycling with the same cycling temperature and interval, crosses around Y=2 3 (in a.u.), except 85C. A higher temperature cycling moves the crossing to longer time and increases the slope. Of course a higher cycling number also increases the slope. In this paper we defined the time offset as the time of extrapolated Vt shift curve have a value of Y=2.5. These phenomena are qualitatively explained by TFM as shown in Fig.3. According to TMF, charge de-trapping occurs from oxide surface and the de-trapping of charges in deep region takes long time. On the other hand in FN tunneling stress, it is known that electrons are trapped uniformly in the gate oxide. Then after the distributed-cycling stress, the electron density near the surface is low and that of deep region, where electrons are only accumulated without de-trapping, is high. It is also known that high temperature accelerates both electron de-trapping from surface and trapping in deep region. Schematic profiles of the trapped electron density after different temperature cycling are shown in Fig.3(a). An electron density profile after high temperature cycling has deeper low-density region and higher density in the deeper region. Corresponding Vt shift curves are shown in Fig.3(b). After higher temperature cycling Vt shift starts after a longer time offset and has a steeper slope. A higher cycling number only increases electron densities in deeper region and results in the steeper slope of Vt shift curve with the same time offset, which is illustrated with dotted lines in the Fig.3(b). . B. Slope analysis Fig.4 shows the Vt shift slope dependence on the cycling interval. The slope seems to be independent of the cycling interval and decided only by the cycling temperature and number. Then average slopes on intervals are used for the slope analysis. Fig.5 shows Arrhenius plots of slopes of the Vt shift curves. The temperature dependence of slope is small and Ea is between 0.03-0.05eV. The pre-exponential factor for 3.6k cycling is two times bigger than that of 1.2k cycling. It may means that a saturation tendency appears after 1.2k cycles. C. Time offset analysis Fig.6 shows the time offset dependence on the cycling interval. The cycling interval dependence of the time offset is almost the same at the temperature lower than 60C, which is m= 0.4. The time offset is independent of the cycling number, except 85C. Temperature acceleration of the time offset is almost the same at the temperature lower than 60C, irrespective of the cycling interval. The temperature dependence has an activation energy of about Ea= 0.5eV. The Ea seems to be larger at the temperature higher than 85C and this tendency becomes larger at the higher cycling number. Conclusions The distributed-cycling experiments were performed including the conditions of a long time interval and low temperature. The dependence of the slope and the time offset of Vt shift curve on the cycling temperature and interval is fully explained by the tunneling front model (TFM). As predicted by TFM, the slope becomes steeper in higher temperature cycling regardless of the cycling interval. The time offset changes with the cycling interval and temperature regardless of the cycling number. Using the parameters which are obtained in this paper, the result of a certain cycling condition can be converted to that of other cycling condition in the temperature range lower than 60C. You do not have to do a long time cycling test to estimate data retention lifetimes with long cycling interval applications. Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, Tsukuba, 2008, -236J-2-2 pp. 236-237

A bipolar-EPROM (BI-EPROM) structure for 3.3 V operation and high speed application

A novel BI-EPROM structure, which has a vertical PNP bipolar transistor in the drain of the conventional EPROM cell, is proposed for future low-voltage and high-speed nonvolatile memories. In the read operation, the large cell current is obtained by the embedded bipolar function. Moreover, since its drain is made of an N-base, it has a high immunity against the soft-write phenomenon and can tolerate a higher channel current. It can be programmed by applying high voltages to both the source and the gate, while the drain is biased 0 V or negative voltage. Its feasibility is confirmed by a test vehicle with a 0.8 mu m technology.<<ETX>>