Hideki Makiyama

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

A 32-bit CPU which operates with the lowest energy of 13.4 pJ/cycle at 0.35V and 14MHz, operates at 0.22V to 1.2V and with 0.14μA sleep current is demonstrated. The low power performance is attained by Reverse-Body-Bias-Assisted 65nm SOTB CMOS (Silicon On Thin Buried oxide) technology. The CPU can operate more than 100 years with 610mAH Li battery.

Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation

We demonstrated Silicon on Thin Buried oxide (SOTB) CMOS especially designed for ultralow-voltage (ULV) operation down to 0.4 V for the first time. Utilizing i) dual-poly gate stack with high-k having quarter-gap work functions best for the ULV CMOS operation, and ii) a novel “local ground plane (LGP)” structure that significantly improves short-channel effect (Vth roll off) without increasing local variability unlike halo for bulk, low-leakage SRAM operation was demonstrated with adaptive-body-bias (ABB) scheme.

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. In this paper, we describe our recent results on the ULV operation of the CPU, SRAM, ring oscillator, and, other logic circuits. Our 32-bit RISC CPU chip, named “Perpetuum Mobile,” has a record low energy consumption of 13.4 pJ when operating at 0.35 V and 14 MHz. Perpetuum-Mobile micro-controllers are expected to be a core building block in a huge number of electronic devices in the internet-of-things (IoT) era.

Reduced drain current variability in fully depleted silicon-on-thin-BOX (SOTB) MOSFETs

Drain current variability in silicon-on-thin-BOX (SOTB) MOSFETs are analyzed by decomposing into current variability components and compared with conventional bulk MOSFETs. It is found that drain current variability in SOTB MOSFETs is largely suppressed thanks to not only reduced VTH variability but also reduced current-onset voltage (COV) variability due to intrinsic channel.

Novel single p+poly-Si/Hf/SiON gate stack technology on silicon-on-thin-buried-oxide (SOTB) for ultra-low leakage applications

We demonstrate a cost effective 65-nm SOTB CMOS technology for ultra-low leakage applications. Novel single p+poly-Si/Hf/SiON gate stack of mid-gap work function and precise GIDL control achieved ultra-low leakage of 0.2 pA/μm, which corresponds to approx. 100nA/chip (100k gate logic). Now the SOTB technology can provide three options from ultra-low voltage to ultra-low leakage that covers a wide variety of applications in the Internet of Things (IoT) era.

Impact of random telegraph noise on write stability in Silicon-on-Thin-BOX (SOTB) SRAM cells at low supply voltage in sub-0.4V regime

The effect of random telegraph noise (RTN) on write stability of SRAM cells in sub-0.4V operation is intensively measured and statistically analyzed. RTN of N-curves in Silicon-on-Thin-BOX (SOTB) cells is monitored. By developing statistical models, it is found that, different from bulk SRAM cells operating at high supply voltage (VDD), fail bit rate (FBR) at sub-0.4V is degraded by RTN. The origin of high FBR due to RTN at sub-0.4V is discussed.

Detailed analysis of minimum operation voltage of extraordinarily unstable cells in fully depleted silicon-on-buried-oxide six-transistor static random access memory

The minimum operation voltage (Vmin) of very unstable cells in silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) static random access memory (SRAM) is analyzed in detail. It is found that the worst cell in 16k SRAM is very unstable and the stability characteristics of the worst cell correspond to approximately 6? from those of the median cell. It is also found that extraordinarily unstable cells are much more sensitive to VTH change than median cells and that the static noise margin (SNM) and Vmin well correlate only in extraordinarily unstable cells. A simple VTH model for evaluating Vmin is developed and validated by Vmin measured in extraordinarily unstable cells.

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (Vdd). In the ultralow-Vdd regime, however, the upsurging delay (τpd) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at Vdd = 0.4 V.

Statistical Analysis of Subthreshold Swing in Fully Depleted Silicon-on-Thin-Buried-Oxide and Bulk Metal--Oxide--Semiconductor Field Effect Transistors

The variability of subthreshold swing (SS) in fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) MOSFETs is statistically analyzed and compared with that of conventional bulk MOSFETs. It is newly found that SS variability is small enough in deep subthreshold region (small drain current Ids) while it increases as increasing Ids. The mechanisms of this behavior is intensively investigated and it is found that the increase in SS variability is caused by current-onset voltage (COV) variability that is due to random dopant fluctuation (RDF). Since SOTB FETs have small COV variability thanks to an intrinsic channel, SS variability is much smaller than bulk FETs, which is a great advantage of FD SOTB in terms of Ion/Ioff ratio.

Statistical analysis of four write stability metrics in fully depleted silicon-on-thin-BOX (SOTB) and bulk SRAM cells at low supply voltage

Statistical distributions of four write stability metrics at low supply voltage (VDD) were measured in 1k fully depleted (FD) silicon-on-thin-BOX (SOTB) and bulk SRAM cells. It is found that butterfly curve shows abnormal “two-mode” distributions, while bit-line and word-line margins maintain good normality even at low VDD, which demonstrates bit-line and word-line margins as preferred write stability metrics.