Yoshiki Yamamoto

Low-resistive and homogenous NiPt-silicide formation using ultra-low temperature annealing with microwave system for 22nm-node CMOS and beyond

A novel NiPt-silicide formation using microwave annealing (MWA) is proposed, and superior properties of NiPt silicide in ultra-shallow junction (USJ) are demonstrated for the first time. MWA is suitable for the thin NiPtSi formation with its stable and ultra-low temperature (less than 250 °C) heating. The anomalous Ni diffusion during the NiPtSi formation is considered to be suppressed because MW system heats Si substrates selectively. As a result, low-resistive and homogeneous NiPtSi can be formed, and the increase of the junction leakage current due to the abnormal NiPt-silicide growth is successfully suppressed in USJ. This superior technique is quite promising for achieving 22nm-node CMOS and beyond.

A novel cylinder-type MIM capacitor in porous low-k film (CAPL) for embedded DRAM with advanced CMOS logics

A novel cylinder-type metal-insulator-metal (MIM) capacitor in porous low-k film (CAPL) is proposed for embedded DRAMs (eDRAMs). The CAPL removes long bypass-contacts (BCT) with high resistance, which have been used to connect transistors with Cu interconnects by way of the MIM capacitor layer. A key technical challenge for the CAPL integration is control of pore structure in the low-k film to avoid metal contamination during the gas-phase deposition of the MIM electrode (BE) on the porous low-k film. A molecular-pore-stack (MPS) SiOCH film (k=2.5) with very small pores (0.4 nm-diameter) is found to be the best candidate for the CAPL structure, applicable to eDRAM with high performance logics for 28 nm-node and beyond.

Design consideration of 0.4V-operation SOTB MOSFET for super low power application

The silicon on thin buried oxide (SOTB) CMOS is suited for ultralow-voltage operation of CMOS circuits, that is required for drastic power reduction of LSIs because of its small variability and adaptive back bias controllability. In this study, we show that the design concept of threshold voltage for ultralow-voltage (V<inf>dd</inf>=0.4V) operation of SOTB. To achieve a good trade-off of I<inf>on</inf> and I<inf>off</inf>, gate work function (Ф<inf>WF</inf>) should be controlled at 4.25–4.35eV and 4.90–5.05eV for N- and P-type MOS-FETs (NMOS and PMOS), respectively. Moreover, higher N<inf>sub</inf> is preferable for increasing I<inf>on</inf>. Our optimized design achieved that I<inf>on</inf> values 170 and 89 µA/µm at I<inf>off</inf> values of 5.6 and 7.8 pA/µm for NMOS and PMOS, respectively. This result indicates that the 0.4-v operation is possible without paying significant speed penalty from the conventional 1-V operation.

A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT

A 65-nm Silicon-on-Thin-Box (SOTB) embedded SRAM is demonstrated. By using back-bias (BB) control in the sleep mode, 13.72 nW/Mbit ultra-low standby power is observed, which is reduced to 1/1000 compared to the normal standby mode. The measured read access time with forward BB is 1.84 ns at 1.0 V overdrive and 25°C, which is improved by 60% and thus we achieved over 380 MHz operation. Up to 20% active read power reduction is also achieved by using proposed localized adoptive wordline width control.

SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive

Ultra low power performance is indispensable for Micro Controller Unit (MCU) used as wireless sensor and communication nodes which needs battery maintenance free and energy harvesting operation in the Internet of things (IoT) era. The Silicon on Thin Buried Oxide (SOTB) is one of the most suitable CMOS technology for ultra low power MCU because of its small variability and back bias controllability. This paper describes the mechanism of ultra low power performance of SOTB, performance demonstration of transistor, SRAM and MCU test chip, and what SOTB will realize for IoT and Automotive. SOTB will have less than 1/10 of power efficiency by low leakage current at standby mode and low current consumption at operation mode which todays technology cannot realize.

V min =0.4 V LSIs are the real with silicon-on-thin-buried-oxide (SOTB) — How is the application with "Perpetuum-Mobile" micro-controller with SOTB?

Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the near- or sub-Vth operation is effective in reducing energy per operation of CMOS circuits, its slow operation speed can miss a chance to be used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ul-tralow-power (ULP) electronics because of its small variability and back-bias control. This paper describes our results on the ULV operation of SRAM and ring oscillator (RO) circuits and shows the operation speed is now sufficiently high for many ULP applications. The “Perpetuum-Mobile” micro-controllers operating at ~0.4 V are expected to be implemented in many applications such as the internet of things.

Performance improvement of metal-gate/high-k CMOS by NiPt-silicidation using laser annealing

NiPt-silicide formation using advanced annealing such as laser annealing (LA) or microwave annealing (MWA) is applied for gate-first metal gate/high-k CMOS. It is found that LA enhances NMOS drive current due to the reduction of parasitic resistance. It is found that LA produces characteristic Pt-distribution and reduces interfacial resistance between NiPtSi and Si especially for NMOS. On the other hand, MWA produces homogeneous NiPt-silicide and suppresses defect density related to contact leakage current.