Tsuneo Inaba

A 64Mb MRAM with clamped-reference and adequate-reference schemes

In order to realize a sub-Giga bit scale NVRAM, the novel MRAM based on the spin-transfer-torque (STT) switching has been intensively investigated due to its excellent scalability compared with a conventional magnetic field induce switching MRAM [1]. However, the memory cell size of STT-MRAM reported so far is still over 1µm2, and the memory capacity is limited to 32Mbit even in almost 100mm2 die size [2]. The large cell size is due to the large switching current of MRAM cells. In order to reduce the cell size, we have proposed the perpendicular tunnel magnetoresistance (P-TMR) device, and have confirmed its high potential to achieve lower switching current [3]. In this paper, a 64Mb STTMRAM with the P-TMR device having the circuit techniques to maximize operational margin is described.

A pseudo multi-bank DRAM with categorized access sequence

A new architecture which realizes the large bandwidth with virtually the same core circuitry as a conventional DRAM is proposed. The improved row block activation scheme combined with a categorized access sequence improves the bandwidth of the DRAM even with the shared sense amplifier scheme. The data efficiency of the random read/write mixed cycle is improved by the proposed delayed write operation, which fills the write to read command gap effectively. The proposed architecture is successfully examined in the 128 Mbit test vehicle fabricated with a 0.15 /spl mu/m CMOS process.

A dual layer bitline DRAM array with Vcc/Vss hybrid precharge for multi-gigabit DRAMs

A dual layer BL array and a Vcc/Vss hybrid precharge sensing scheme has been proposed. The array affords the maximum memory cell density and relaxed sense amplifier layout which is as wide as the conventional folded BL sense amplifier layout. The Vcc/Vss hybrid precharge scheme gives the doubled operation voltage for sensing compared with the conventional half Vcc precharge method without the BL charge/discharge current increase.

A 16Mb MRAM with FORK Wiring Scheme and Burst Modes

A 16Mb MRAM based on 0.13mum CMOS and 0.24mum MRAM process achieves a 34ns asynchronous access and 100MHz synchronous operation, compatible with pseudo-SRAM for mobile applications. By implementation of FORK wiring scheme, the cell efficiency is raised to 39.9% and the disturb robustness of half-selection state is improved

1.8 V Power Supply 16 Mb-MRAMs With 42.3% Array Efficiency

Technologies for realizing high density MRAM were developed. First, new circuitry to lower the resistance of programming wires was developed. Second, both MTJ plane shape and cross-sectional structure were optimized to lower the programming current. Based on these two technologies, 16 Mb MRAM was designed, fabricated with 130 nm CMOS process and 240 nm back end MTJ process. As a result, a 1.8 V power supply MRAM with 42.3% array efficiency was successfully demonstrated

Resistance ratio read (R/sup 3/) architecture for a burst operated 1.5V MRAM macro

A novel resistance ratio read (R/sup 3/) architecture for a magnetoresistive random access memory (MRAM), which realizes a burst read operation and higher fluctuation immunity of MTJ resistance, is proposed. In this architecture, a memory cell consists of 2 transistors and 2 MTJs, which store the complementary data, and the intermediate node between these MTJs is connected to a sense amplifier. The readout signal is proportional to the ratio of 2 MTJ resistances. The proposed R/sup 3/ architecture provides a simple read system which enables the introduction of a burst read mode. This architecture has a higher fluctuation immunity of MTJ resistance compared with the conventional current signal read scheme. Moreover, the proposed architecture can easily modify the macro specification to satisfy the demands of the customer, because the burst length and random access time are adjustable by the dimensions of the memory cell array.

23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture

Spin-transfer torque magnetic RAM (STT-MRAM) is one of the most promising nonvolatile memories with guaranteed high-speed read and write operations. Along with performance improvements in the tunnel magnetoresistance (TMR) and the magnetic tunnel junctions (MTJ) required switching current, there have also been reports on high-capacity (up to tens of Mb) STT-MRAM [1–4]. In [2] a perpendicular-TMR (pMTJ) device is used to reduce the switching current and a high-speed current sense amplifier is proposed. In [3] a 54nm 2T-1MTJ 14F2-cell is proposed that uses a high-density DRAM process: self-aligned contact and plug process. However, the unit cell area of STT-MRAM is still much larger than that of DRAM, making STT-MRAM not cost-competitive to contemporary DRAM.

A 250 mV bit-line swing scheme for a 1 V 4 Gb DRAM

We have proposed a new 1/4 Vcc bit-line swing architecture and related sense amplifier for 1 V 4 Gb DRAM and beyond. These schemes reduce power dissipation to 40% without degradation of the read-out signal and also improve device reliability.