Kazumi Inoh

Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant

Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibility

Fully-depleted (FD) floating body cell on 55nm SOI featuring excellent logic process compatibility has been successfully developed. For the first time FD operation is reported through significant signal enlargement by negative substrate bias. Using standard salicide process and FD operation, high-density embedded memory on SOI is achievable.

A novel lateral bipolar transistor with 67 GHz f/sub max/ on thin-film SOI for RF analog applications

In this paper, a novel lateral bipolar transistor on thin film silicon-on-insulator (SOI) is presented. With a small emitter size of 0.12/spl times/3.0 /spl mu/m/sup 2/, low base resistance of 270 /spl Omega/ due to a novel Co silicided base electrode and low base-collector parasitic capacitances of 1.4 fF due to SOI material, it achieves the highest f/sub max/ of 67 GHz among SOI bipolar transistors. Also, the low emitter-base capacitance of 1.5 fF and the low collector-substrate capacitance of 2.5 fF are realized. The transistor has a simple structure, which is fabricated with simplified processes without any new sophisticated technologies, excluding trench isolation and epitaxial base used in current bipolar transistors. This can lower the fabrication cost of transistors. We have demonstrated the possibility of lateral bipolar transistor on thin film SOI as next-generation device for RF analog applications.

Highly scalable FBC (Floating Body Cell) with 25nm BOX structure for embedded DRAM applications

A novel FBC with 25nm-thick BOX (buried oxide) structure has been developed. A feature of new FBC is scalability in the case of thinner SOI, which promises embedded DRAM on SOI in future generations. Using 96Kbit array, the pause time distribution of FBC is demonstrated for the first time. Due to simplified structure, pause time variation of new FBC is significantly suppressed compared with conventional FBC.

A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability

A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The well design has been optimized both for the array device and the peripheral circuit in order to realize full functionality and good retention characteristics. Cu wiring has been used for the bit line and the source line, which increases the signal of the worst bit in the array and also realizes full compatibility with the standard CMOS process. Scalability of FBC down to 45-nm CMOS technology node has been investigated by a device simulation. The signal and the maximum electric field can be maintained constant with the reduction of the device dimensions and the operation voltage

A 31 GHz f/sub max/ lateral BJT on SOI using self-aligned external base formation technology

A novel device structure and simple process technology for realizing low-power/high-performance SOI lateral BJTs are presented. Low base resistance has been achieved by employing a self-aligned external base formation process. Due to reduced parasitics, the fabricated device exhibited an f/sub max/ of 31 GHz, the highest value for an SOI BJT reported so far.

A floating body cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM

A 128Mb SOI DRAM with FBC (floating body cell) has been successfully developed for the first time. Two technologies have been newly implemented. (i) In order to realize full functionality and good retention characteristics, the well design has been optimized both for the array device and the peripheral circuit. (ii) Cu wiring has been used for bit line (BL) and source line (SL), which leads to increasing the signal of the worst bit in the array and also realizes the full compatibility with 90nm CMOS technology

An 0.3-/spl mu/m Si epitaxial base BiCMOS technology with 37-GHz f/sub max/ and 10-V BV/sub ceo/ for RF telecommunication

In this paper, a 0.3-/spl mu/m BiCMOS technology for mixed analog/digital application is presented. A typical emitter area of this technology is 0.3 /spl mu/m/spl times/1.0 /spl mu/m. This technology includes high f/sub max/ of 37 GHz at the low collector current of 300 /spl mu/A and high BV/sub ceo/ of 10 V NPN transistor, CMOS with L/sub eff/=0.3 /spl mu/m, and passive elements. By using the shallow and deep trench isolation technology and nonselective epitaxial intrinsic base, the C/sub jc/ can be reduced to 1.6 fF, which is the lowest value reported so far. As a results, we have managed to obtain the high f/sub max/ at the low current region and high BV/sub ceo/ concurrently. These features will contribute to the development of high-performance BiCMOS LSIs for various mixed analog/digital applications.

Analysis on high-frequency characteristics of SOI lateral BJTs with self-aligned external base for 2-GHz RF applications

High-frequency characteristics of SOI lateral BJTs designed for 2-GHz radio frequency (RF) applications are measured and compared for various link-base length, emitter width, and collector structure. Based on experimental data and device simulation, degradation mechanism of cutoff frequency for shorter link-base is analyzed. By suppressing external base-induced effects, peak cutoff frequency is increased from 10 GHz to 15 GHz.

Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure

In this paper, we demonstrate that the sidewall spacer thickness of double polysilicon self-aligned bipolar transistor structure is one of the fundamental limitations in bipolar transistor scaling by using an accurate small signal equivalent circuit. The simulated results show that the maximum fT reduces to half when the sidewall spacer thickness reduces from 0.1μm t o 0.025μm.