Tomoki Higashi

Memory design using one-transistor gain cell on SOI

A 512 kb DRAM has a 7F/sup 2/ one-transistor gain cell (F=0.18 /spl mu/m) on SOI. The array driving method makes selective write possible. Basic operation is verified by device simulation and hardware measurement. Simulations show 40 ns access time. Non-destructive readout and Cb/Cs-free signal development improve cell efficiency.

Autonomous refresh of floating body cell (FBC)

Physics of autonomous refresh of FBC is presented. Current input to the floating body by impact ionization and output by charge pumping can balance to make FBC refresh by itself without sense amplifier operation. Thanks to this feature, multiple cells on a BL can be refreshed simultaneously, leading to a drastic reduction of BL charging current compared to the conventional refresh. 600 muA refresh current for 1 G-bit memory is achieved in 32 nm technology node with 4 ms retention time. If gate direct tunneling current is used as output, FBC can realize static RAM without periodical refresh when retaining data.

Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant

Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibility

Fully-depleted (FD) floating body cell on 55nm SOI featuring excellent logic process compatibility has been successfully developed. For the first time FD operation is reported through significant signal enlargement by negative substrate bias. Using standard salicide process and FD operation, high-density embedded memory on SOI is achievable.

A single-chip 802.11a MAC/PHY with a 32 b RISC processor

An 802.11a compliant MAC/PHY processing chip has been successfully fabricated in 0.18 /spl mu/m CMOS. Thirty million transistors are integrated on a 10.91 /spl times/ 10.91 mm/sup 2/ die in a 361-pin PFBGA. The MAC functions are fully implemented by firmware on an embedded 32 b RISC processor and hardware acceleration logic. The PHY supports a complete set of data rates up to 54 Mb/s.

Scaling scenario of floating body cell (FBC) suppressing V th variation due to random dopant fluctuation

A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the Vth variation of cell array transistors is mainly attributed to the random dopant fluctuation in channel region. By setting the channel impurity concentration in the order of 1016cm-3 or lower, Gbit array functionality is guaranteed for the 32nm node and further scaled generations.

FBC's Potential of 6F 2 Single Cell Operation in Multi-Gbit Memories Confirmed by a Newly Developed Method for Measuring Signal Sense Margin

A 6F2 single cell (one-cell-per-bit) operation of the floating body RAM (FBRAM) is successfully demonstrated for the first time with more than 60% yield of 16Mbit area in a wafer. The signal sense margin (SSM) at actual read conditions is found to well back up the functional results. The parasitic resistance in the source and drain formed under the FBCs spacers can be optimized for making the SSM as large as 8muA at plusmn 4.5sigma without sacrificing the retention time.

Array architecture of floating body cell (FBC) with quasi-shielded open bit line scheme for sub-40nm node

Cell array architecture for floating body RAM of 35 nm bit line half pitch is described. The quasi-non-destructive-read-out feature of floating body cell contributes to eliminating inter-bit line coupling noise in open bit line architecture without degrading the cycle time of the RAM.

A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability

A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The well design has been optimized both for the array device and the peripheral circuit in order to realize full functionality and good retention characteristics. Cu wiring has been used for the bit line and the source line, which increases the signal of the worst bit in the array and also realizes full compatibility with the standard CMOS process. Scalability of FBC down to 45-nm CMOS technology node has been investigated by a device simulation. The signal and the maximum electric field can be maintained constant with the reduction of the device dimensions and the operation voltage

Autonomous Refresh of Floating-Body Cell due to Current Anomaly of Impact Ionization

Physics of autonomous refresh is presented, which explains the mechanism of a spontaneous recovery of degraded binary states of the floating-body cell (FBC). Input current to the floating body and output current from the body balance to generate an unstable stationary state that is accompanied by two stable stationary ones. The current anomaly of impact ionization is essential for the instability that brings about the bistability and is realized by positive feedback where impact ionization current input increases as the body voltage increases. Experiments with charge pumping current as output show that the autonomous refresh is possible on a single-cell basis. Necessary conditions for a high-density memory to be autonomously refreshed are derived and assessed for state-of-the-art FBCs. FBC is shown in simulation to become an SRAM cell when the autonomous refresh is applied, which uses gate direct tunneling current as output. This is an SRAM cell that is theoretically expected to have the simplest structure ever reported.