Hiroto Kitabayashi

100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology

This paper describes the 100-Gb/s multiplexing operation of a selector IC and demultiplexing operation of a D-type flip-flop (D-FF) using production-level 0.1-/spl mu/m-gate-length InP HEMT IC technology. To boost the operating speed of the selector IC, a selector core circuit directly drives an external 50-/spl Omega/ load, and is included in the output stage. In addition, a test chip containing the selector and a D-FF to confirm error-free operation of these circuits was designed. The fabricated selector IC exhibited clear eye openings at 100 Gb/s, and its error-free operation was confirmed by using the test chip.

Photoreceiver module using an InP HEMT transimpedance amplifier for over 40 gb/s

We developed a photoreceiver module for over 40 Gb/s that uses two ultrahigh- speed device technologies: an InP HEMT transimpedance amplifier (TIA) and a uni-traveling-carrier photodiode (UTC-PD). The TIA was designed to have a wide dynamic range by using cascade HEMT topology for the output buffer. We found that reducing the standing wave at the PD-TIA interface by decreasing the change of arg(S/sub 11/) of the TIA within the required frequency region is important for increasing the bandwidth of the module. We obtained a minimum sensitivity of -7.6 dBm and a dynamic range of 11 dB for 43-Gb/s nonreturn-to-zero optical input signal. Error-free operation of the module was confirmed at a data rate of 50 Gb/s.

50-gbit/s InP HEMT 4 : 1 multiplexer/1 : 4 demultiplexer chip set with a multiphase clock architecture

A 50-Gbit/s InP high electron-mobility transistor (HEMT) chip set of 4 : 1 multiplexer (MUX) and 1 : 4 demultiplexer (DMUX) integrated circuits (ICs) with a multiphase clock (MPC) architecture is described. The MPC architecture employs a quarter-rate four-phase clock generated by a toggle flip-flop inside the ICs, which reduces the number of circuit elements and lowers the power consumption. The fabricated 4 : 1 MUX and 1 : 4 DMUX ICs exhibited 50-Gbit/s error-free operations for 2/sup 31/-1 pseudorandom bit sequences with 1.71- and 1.42-W power consumption, respectively. Compared to conventional tree-type 4 : 1 MUX and 1 : 4 DMUX ICs using InP HEMTs, the MPC 4 : 1 MUX and 1 : 4 DMUX ICs operate at the same operating speed with less than one-third power consumption.

1.4-W 50-Gbit/s InP HEMT 1:4 demultiplexer IC with a multi-phase clock architecture

High-speed and low-power operation of a 1:4 demultiplexer IC with a multi-phase clock (MPC) architecture is reported. The architecture features four parallel latch lines and a toggle flip-flop (TFF) that generates a four-phase clock. The IC, which was fabricated using InP HEMTs, exhibited 50-Gbit/s error-free operation with a power consumption of 1.42 W. Compared to a conventional tree-type InP HEMT 1:4 demultiplexer IC, the IC with the MPC architecture operates at the same operating speed with only one-quarter the power consumption.

Optical receiver module using an InP HEMT transimpedance amplifier for over 40 Gbit/s

We developed an optical receiver module for over 40 Gbit/s that uses two ultra-high-speed device technologies: an InP HEMT transimpedance amplifier (TIA) and a uni-travelling-carrier photodiode (UTC-PD). We introduced a new design criterion for the interface between the PD and TIA in order to obtain sufficient bandwidth. We confirmed error-free operation of the optical receiver module for a 50 Gbit/s non-return-to-zero optical input signal.

InP HEMT IC technology for 40 Gbit/s and beyond

InP-based HEMT integrated circuit (IC) technology has contributed much to the research and development of highspeed optical communications systems and microwave/millimeter-wave wireless systems. This paper describes recent progress in our InP HEMT IC technology for 40 Gbit/s optical communications systems and discusses future prospects for 100 Gbit/s and beyond.