Kenneth T. Settlemyer

Improving yield through the application of process window OPC

As the industry progresses toward more challenging patterning nodes with tighter error budgets and weaker process windows, it is becoming clear that current single process condition Optical Proximity Corrections (OPC) as well as OPC verification methods such as Optical Rules Checking (ORC) performed at a single process point fail to provide robust solutions through process. Moreover, these techniques can potentially miss catastrophic failures that will negatively impact yield while surely failing to capitalize on every chance to enhance process window. Process-aware OPC and verification algorithms have been developed [1,2] that minimize process variability to enhance yield and assess process robustness, respectively. In this paper we demonstrate the importance of process aware OPC and ORC tools to enable first time right manufacturing solutions, even for technology nodes prior to 45nm such as a 65nm contact level, by identifying critical spots on the layout that became significant yield detractors on the chip but nominal ORC could not catch. Similarly, we will demonstrate the successful application of a process window OPC (PWOPC) algorithm capable of recognizing and correcting for process window systematic variations that threaten the overall RET performance, while maintaining printed contours within the minimum overlay tolerances. Direct comparison of wafer results are presented for two 65nm CA masks, one where conventional nominal OPC was applied and a second one processed with PWOPC. Thorough wafer results will show how our process aware OPC algorithm was able to address and successfully strengthen the lithography performance of those areas in the layout previously identified by PWORC as sensitive to process variations, as well as of isolated and semi-isolated features, for an overall significant yield enhancement.

Time-dependent dielectric breakdown evaluation of deep trench capacitor with sidewall hemispherical, polysilicon grains for gigabit DRAM technology

The continued scaling of DRAM cell sizes requires maintaining a sufficiently high storage capacitance per cell. Capacitance enhancement technique using hemispherical-polysilicon grains (HPG) in deep trench capacitors has been previously reported for the continued scaling of deep trench DRAM technology. In this paper, the reliability aspects of such HPG deep trench capacitors are critically investigated. The operational lifetime, based on constant voltage stressing, demonstrates the feasibility of such capacitors for gigabit DRAM applications.

Novel techniques for scaling deep trench DRAM capacitor technology to 0.11 /spl mu/m and beyond

In this paper we discuss the use of area enhancement techniques to increase capacitance while minimizing node leakage in 0.11 /spl mu/m deep trench capacitors. The thinning of conventional SiN/SiO/sub 2/ dielectric is discussed and its effectiveness for future generations assessed. Other capacitance enhancement schemes examined rely on independently enhancing the capacitor surface area while retaining the critical dimensions of the trench top with a protective SiN film. Area enhancement schemes reviewed include bottling of non-rotated and rotated wafers-(100) notch-aligned, and hemispherical-grained silicon deposition. We have demonstrated these capacitance enhancement techniques on 0.11 /spl mu/m ground rules, and have achieved more than 55% capacitance enhancement while still maintaining less than 1 fA/cell leakage. We also report reliable operational lifetimes on capacitance enhanced structures. The scalability of these area enhancement techniques is examined.

Ultra-thin SOI replacement gate CMOS with ALD TaN/high-k gate stack

We have demonstrated aggressively scaled high performance UTSOI replacement gate CMOS featuring a HfO/sub 2//TaN gate stack which achieves T/sub inv/ of 17.5nm with greater than 100 times reduction in leakage compared to a SiON/poly-Si control sample. The atomic layer deposition process, used for the metal gate electrode material, enables the replacement gate structure to be robust at extremely small dimensions. An offset spacer together with the ultra-thin Si channel is used to demonstrate functional sub-25nm UTSOI replacement gate pFETs with high-k and metal gate for the first time. These results suggest that the replacement gate architecture is a viable option for future high performance CMOS technologies.

Technologies for scaling vertical transistor DRAM cells to 70 nm

Vertical transistor DRAM cells have been demonstrated as viable in the 110 nm generation. This paper describes the issues associated with scaling these cells to the 70 nm node and demonstrates fixes to all known issues. Scaling to 70 nm is possible through the development of two key enabling technologies, high aspect ratio STI fill and low resistance metal deep trench fill, and through minor cell modification. Each of these items are addressed and shown to be viable using a functional 512 Mb prototype DRAM chip at 110 nm half-pitch groundrule. Based on these results, we believe the vertical transistor DRAM cell is one of the most promising for continued scaling of conventional DRAM and embedded DRAM cells.