Hisanori Hamano

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

A 4-Mb cache dynamic random access memory (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, is described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7- mu m CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm/sup 2/ is only a 7% increase over the conventional 4-Mb DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity. >

A CAD compatible SOI/CMOS gate array having body-fixed partially-depleted transistors

This 0.35/spl mu/m 220kG SOI/CMOS gate array uses partially-depleted devices and allows use of cell libraries and design methods compatible with bulk/CMOS gate arrays by optimizing the basic-cell layout and power-line wiring. The SOI/CMOS gate array operates at 2.0V consuming 65% less power than typical 0.35/spl mu/m 3.3V bulk/CMOS gate arrays.

A delay-locked loop and 90-degree phase shifter for 100 Mbps double data rate memories

Recent high-speed DRAMs adopt the architecture known as DDR (Double Data Rate) in which data are sent out at both rising and falling edges of the system clock. In order to capture the incoming data, the 90-degree phase shifter is used to shift the phase of the system clock to the center of the data period. Conventional 90-degree shifters have been organized from the PLL. In this paper, the 90-degree phase shift is achieved without a PLL. This shifter is also able to reduce the influence of the clock duty error.

A 0.35 /spl mu/m 560 KG SOI/CMOS gate array using field-shield isolation technique

Summary form only given. SOI/CMOS devices have been developed not only for memory LSIs but also for logic LSIs. Some of the recent works include gate arrays having 220-320 K usable gates and operating at a 2.0 V supply voltage. As the history of bulk/CMOS devices indicate, the market will demand SOI/CMOS gate array to integrate more and more gates and operate at lower and lower supply voltages to reduce power consumption. This paper describes a 1.0 V 560 KG SOI/CMOS gate array using 0.35 /spl mu/m partially-depleted transistors to meet this demand. The field-shield isolation technique stabilizes the body potential of transistors sufficiently to suppress the floating-body problems. Also the technique eliminates the leakage current flowing through the transistor edge to suppress the standby current under sub-threshold leakage-level.

A floating-point divider using redundant binary circuits and an asynchronous clock scheme

This paper describes a new floating-point divider (FDIV) using redundant binary circuits on an asynchronous clock scheme for an internal iterative operation. The redundant binary representation of +1=(1,0), 0=(0,0), -1+(0,1) is applied to the all mantissa division circuits. The simple and unified representation reduces circuit delay for the quotient determination. Additionally, the asynchronous clock reduces a clock margin overhead. The architecture design avoids post processes, whose main role is to produce the floating-point status flags. The FDIV core using proposed technologies operates at 42.1 ns with 0.35 /spl mu/m CMOS technology and triple metal interconnections. The small core of 13.5 k transistors is laid-out in 730 /spl mu/m/spl times/910 /spl mu/m area.