S. Maegawa

A 1 V 46 ns 16 Mb SOI-DRAM with body control technique

Low-voltage and low-power DRAMs of appropriate capacity are required for portable systems such as portable PCs and Personal Digital Assistants (PDAs). Though a 1.2 V 49 ns bulk-DRAM has been reported, still lower voltage operation is difficult for bulk-DRAMs, due to the back bias effect and large junction capacitance. SOI devices have several advantages over bulk devices, such as small subthreshold swing (S-factor), elimination of the back bias effect, and small junction capacitance. To utilize these advantages, many SOI-DRAM studies and proposals have been made. The basic operation of the SOI-DRAM at 2.3 V has been examined using an experimental 64 kb SOI-DRAM, and a 3 V 50 ns 16 Mb SOI-DRAM has been also reported. Here the authors present a 1 V 46 ns 16 Mb SOI-DRAM which uses a 0.5 /spl mu/m CMOS/SIMOX process. To accelerate low-voltage speed, a body-pulsed sense amplifier (BPS) and body-driven equalizer (BDEQ) are used. The conventional body-control technique uses partially-depleted (PD) transistors. In contrast, fully-depleted (FD) transistors are used to reduce leakage current in the off-state.

Impact of actively body-bias controlled (ABC) SOI SRAM by using direct body contact technology for low-voltage application

Actively Body-bias Controlled (ABC) SOI SRAM that has a new cell structure including connections of the access and the driver transistors bodies to the word line is proposed to realize low-voltage operation. We developed the direct body contact technology to apply forward biases to the bodies without area penalties and increases of parasitic gate capacitances by using the hybrid trench isolation for the first time. Moreover, the standby current does not change because the body bias is not applied when the word-line voltage is low level. It is successfully demonstrated that low-voltage and high-speed operation is achieved by using the ABC SOI SRAM.

Impact of 0.10 /spl mu/m SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

A hybrid-trench-isolation (HTI) technology is proposed to overcome the scaling limitations caused by the difficulty of gate thinning and increased soft error rate at the 0.1 /spl mu/m era. It is revealed that a significant speed improvement against bulk is achieved by using the body-tied structure without floating-body-relate speed deterioration. A two-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAM was demonstrated as compared with bulk structure. Moreover, it is shown that full trench isolation in the HTI offers excellent isolation characteristics to realize the one-chip integration of analog and digital LSIs. It is concluded that SOI technology with HTI structure is one of the solutions against the scaling limitations.

A CAD compatible SOI/CMOS gate array having body-fixed partially-depleted transistors

This 0.35/spl mu/m 220kG SOI/CMOS gate array uses partially-depleted devices and allows use of cell libraries and design methods compatible with bulk/CMOS gate arrays by optimizing the basic-cell layout and power-line wiring. The SOI/CMOS gate array operates at 2.0V consuming 65% less power than typical 0.35/spl mu/m 3.3V bulk/CMOS gate arrays.

Bulk-layout-compatible 0.18 /spl mu/m SOI-CMOS technology using body-fixed partial trench isolation (PTI)

Transistor performance improvement has been strongly required for work toward highly integrated intelligent system LSIs. To meet this demand, silicon on insulator (SOI) has become of major interest for next generation devices, because it can offer durable device scaling as compared with bulk devices (Schepis et al. 1997). The critical issues for SOI are floating-body effects such as deterioration in drain current (Matsumoto et al. 1999), dynamic threshold voltage instability (Lu et al. 1997), and increased soft error rate (Wada et al. 1998). These have restricted the application of floating SOI, especially to analog circuits. Some circuit modifications and body contact insertions are necessary. A full body-fixing structure is another approach and some techniques have been proposed (Koh et al. 1997; Iwamatsu et al. 1995). However, when using these techniques, there have been some shortcomings in terms of scalability and layout compatibility. In this report, we propose a partial trench isolation (PTI) technique in which the body potential is fixed through the region under the trench oxide. With the PTI technology, we can eliminate floating-body effects while maintaining SOI-inherent merits and can realize scalable deep sub-quarter micron LSIs using accumulated bulk-design properties without layout modification. Moreover, the feasibility for ULSIs is demonstrated by a fully functional 4 Mbit SRAM.

Suppression of delay time instability on frequency using field shield isolation technology for deep sub-micron SOI circuits

It was demonstrated that Field Shield (FS) isolation technology can suppress the delay time instability depending on operating frequency. FS isolation technology has been proposed to tie the body potential without any area penalties in gate array. Moreover, the effect of body resistance on the instability was also investigated using device simulation.

70 nm SOI-CMOS of 135 GHz f/sub max/ with dual offset-implanted source-drain extension structure for RF/analog and logic applications

We achieved 135 GHz f/sub max/ and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of V/sub th/ variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.

Feasibility of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

A 0.18 /spl mu/m silicon on insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology using hybrid trench isolation with high resistivity substrate is proposed and its feasibility for embedded RF/analog applications is demonstrated. The hybrid trench isolation is a combination of partial trench isolation and full trench isolation. In the partial trench isolation region, a part of the SOI layer remains under the field oxide so as to provide scalable body-tied SOI metal-oxide-semiconductor field-effect transistors (MOSFETs), while in the full trench isolation region, the whole of the SOI layer is replaced by the field oxide so as to provide high quality passives. It is demonstrated that this technology improves the maximum oscillation frequency and the minimum noise figure of the MOSFET and the Q-factor of the inductor, compared with bulk technology. Moreover, it is verified that the partial-trench-isolated body-tied structure suppresses the floating body effect of SOI devices for RF/analog applications and thus guarantees low-noise characteristics, stability, linearity, and reliability. It is concluded that this technology will be one of the key technologies for supporting the evolution of wireless communications.

An artificial fingerprint device (AFD) module using poly-Si thin film transistors with logic LSI compatible process for built-in security

An artificial fingerprint device module using polycrystalline silicon thin film transistors with logic LSI compatible process is proposed for securing a digital society. Substituting for actual fingerprint characteristics variation of polysilicon thin film transistors is utilized. The variation is random and offers unique, nonalterable, and nonduplicable numbers. Stable recognition operation based on the nature of polysilicon TFTs is suggested.

Direct Measurement of Transient Drain Currents in Partially-Depleted SOI N-Channel MOSFETs Using a Nuclear Microprobe for Highly Reliable Device Designs

Transient drain currents caused by proton microprobe irradiations in partially-depleted (PD) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) were analyzed for soft-error issues. Transient currents of the body-tied MOSFETs can be lowered compared to those of the floating body SOI MOSFETs by suppression of the floating body effect. The effectiveness of the body-tie structure was analyzed by device simulation. Increase in the body potential by proton irradiation is suppressed efficiently in the narrow-channel body-tied SOI MOSFETs due to the low body resistance to excess carrier extraction. On the other hand, the body potential of narrow-channel floating body SOI MOSFETs increase to higher levels than those of the wide-channel MOSFETs due to the lower body capacitance. It is indicated that narrow-channel body-tied SOI MOSFETs are suitable for highly reliable devices. Moreover, a more reliable body-tied structure with high impurity concentration in the body regions to reduce the body resistance in the structure is proposed. The collected drain charge was able to be reduced by utilizing this structure. These devices are expected to be applied to highly reliable LSIs used for satellite systems, server and mainstream LSI applications of the multimedia era.