Beom-jun Jin

The effects of TaN thickness and strained substrate on the performance and PBTI characteristics of poly-Si/TaN/HfSiON MOSFETs

The effects of TaN metal-gate thickness on the electrical characteristics of poly-Si/metal-gate/HfSiON MOSFETs have been investigated. Too thin TaN was reactive with poly-Si gate, which led to the formation of Si-doped metal gate. As a result, the work function of the metal gate was reduced and the capacitance increased while generating traps in HfSiON films. P-MOSFET using poly-Si/TaN gate with channel engineering in strained-Si substrate showed threshold voltage of - 0.45 V at W/L= 10/1 /spl mu/m and improved MOSFET characteristics.

Front-end-of-line (FEOL) optimization for high-performance, high-reliable strained-Si MOSFETs; from virtual substrate to gate oxidation

Front-end-of-line (FEOL) process parameters including virtual substrate (Si/Si/sub 1-x/Ge/sub x/), shallow-trench-isolation (STI) process, and gate oxidation have strong effects on performance and reliability of strained-Si MOSFETs such as gate oxide integrity (GOI), threshold voltage (V/sub TH/ roll-off, reliability behavior including junction breakdown and device isolation characteristics. It is found that gate oxide integrity can be improved by 1 order of magnitude by applying low-temperature, plasma oxidation process as compared with thermal oxidation, junction leakage and device isolation characteristics can be improved by 1 order of magnitude and by two times, respectively, by using low-defect virtual substrate and further defect-curing process, and parameters related with STI process such as thin SiN layer and oxide densification temperature must be optimized both to reduce junction leakage current and to improve device performance such as Ion-Ioff characteristics.

DRAM scaling-down to 0.1 /spl mu/m generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plug

As DRAM downscaling approaches the 0.1 /spl mu/m generation, problems related to transistor short channel effects, storage capacitance, gap filling of high aspect ratio patterns, and leakage currents through each module must be solved. Among these, processing around the storage node self-aligned contact (SAC) is the most critical problem for integration of capacitor-on-bitline (COB) DRAM devices because it is one of the deepest contacts with high aspect ratio; and it reaches the cell transistor junction. However, few reports have addressed this issue, while others have been reported elsewhere (Song et al., 2000; Jeong et al., 2000; Won et al., 2000; Kim et al., 2000). In this paper, a novel process of bitline spacerless storage node SAC and Ru-Ta/sub 2/O/sub 5/-Ru (RIR) capacitor with TiN contact plug is studied for the integration of 0.1 /spl mu/m design-rule based DRAMs. It was found that the spacerless SAC process made downscaling to the 0.1 /spl mu/m design-rule possible and also that it has better electrical properties than the conventional SAC.