Hye-Lan Lee

A highly manufacturable MIPS (metal inserted poly-Si stack) technology with novel threshold voltage control

The novel technique to control the V/sub th/ of n/pMOS for HfSiO(N) in both poly-Si and MIPS (metal inserted poly-Si stack) gates is demonstrated. By adding AlO/sub x/ on HfSiO prior to poly-Si deposition, we successfully achieve symmetrical V/sub th/, values of 0.52V (nMOS), /-0.51V (pMOS) and high performance as I/sub on/, of 423uA/um for nMOS and 207uA/um for pMOS at I/sub off/=20pA/um. In addition, we find out that the ultra-thin and conformal TaN layer in MIPS gate does not contribute to the gate work function. By optimizing the TaN thickness, similar V/sub th/ values, compared to poly-Si gate, are achieved. Consequently, the measured saturation currents at I/sub off/=20pA/um are 430uA/um for nMOS and 250uA/um for pMOS. Both issues of PBTI for HfSiO/AlO/sub x//poly-Si structure and NBTI for HfSiO/AlO/sub x//MIPS structure are resolved by optimizing the post deposition annealing condition and using ozone interfacial oxide, respectively.

Excellent electrical characteristics of lanthanide (Pr, Nd, Sm, Gd, and Dy) oxide and lanthanide-doped oxide for MOS gate dielectric applications

In this paper, we report on an investigation of the electrical characteristics of various amorphous lanthanide oxides prepared by e-beam evaporation. Excellent electrical characteristics were found for the amorphous lanthanide oxide including a high oxide capacitance, low leakage current, and high thermal stability. We also confirmed the excellent thermal stability and mobility characteristics of lanthanide silicate (PrSi/sub x/O/sub y/). In addition, lanthanide-doped HfO/sub 2/ also exhibited a significant reduction in leakage current at the same equivalent oxide thickness.

The effects of TaN thickness and strained substrate on the performance and PBTI characteristics of poly-Si/TaN/HfSiON MOSFETs

The effects of TaN metal-gate thickness on the electrical characteristics of poly-Si/metal-gate/HfSiON MOSFETs have been investigated. Too thin TaN was reactive with poly-Si gate, which led to the formation of Si-doped metal gate. As a result, the work function of the metal gate was reduced and the capacitance increased while generating traps in HfSiON films. P-MOSFET using poly-Si/TaN gate with channel engineering in strained-Si substrate showed threshold voltage of - 0.45 V at W/L= 10/1 /spl mu/m and improved MOSFET characteristics.

Improvement of Performance and Data Retention Characteristics of Sub-50nm DRAM by HfSiON Gate Dielectric

For the first time, we have successfully integrated HfSiON gate dielectric to DRAM and obtained excellent data retention time. Lower gate leakage current and better mobility of HfSiON than plasma nitrided oxide resulted in a 22% smaller propagation delay measured at CMOS inverter as well as one order of magnitude lower stand-by current for DRAM. Optimized gate poly-Si reoxidation and high Vt of HfSiON cell Tr increased DRAM data retention time as much as 2 times longer than plasma nitrided oxide. We demonstrated that HfSiON could enhance performance and be beneficial to date retention time of high thermal budget DRAM at the same time.

Front-end-of-line (FEOL) optimization for high-performance, high-reliable strained-Si MOSFETs; from virtual substrate to gate oxidation

Front-end-of-line (FEOL) process parameters including virtual substrate (Si/Si/sub 1-x/Ge/sub x/), shallow-trench-isolation (STI) process, and gate oxidation have strong effects on performance and reliability of strained-Si MOSFETs such as gate oxide integrity (GOI), threshold voltage (V/sub TH/ roll-off, reliability behavior including junction breakdown and device isolation characteristics. It is found that gate oxide integrity can be improved by 1 order of magnitude by applying low-temperature, plasma oxidation process as compared with thermal oxidation, junction leakage and device isolation characteristics can be improved by 1 order of magnitude and by two times, respectively, by using low-defect virtual substrate and further defect-curing process, and parameters related with STI process such as thin SiN layer and oxide densification temperature must be optimized both to reduce junction leakage current and to improve device performance such as Ion-Ioff characteristics.