Hong-Jyh Li

Nucleation and growth study of atomic layer deposited HfO2 gate dielectrics resulting in improved scaling and electron mobility

HfO2 films have been grown with two atomic layer deposition (ALD) chemistries: (a) tetrakis(ethylmethylamino)hafnium (TEMAHf)+O3 and (b) HfCl4+H2O. The resulting films were studied as a function of ALD cycle number on Si(100) surfaces prepared with chemical oxide, HF last, and NH3 annealing. TEMAHf+O3 growth is independent of surface preparation, while HfCl4+H2O shows a surface dependence. Rutherford backscattering shows that HfCl4+H2O coverage per cycle is l3% of a monolayer on chemical oxide while TEMAHf+O3 coverage per cycle is 23% of a monolayer independent of surface. Low energy ion scattering, x-ray reflectivity, and x-ray photoelectron spectroscopy were used to understand film continuity, density, and chemical bonding. TEMAHf+O3 ALD shows continuous films, density >9g∕cm3, and bulk Hf–O bonding after 15 cycles [physical thickness (Tphys)=1.2±0.2nm] even on H-terminated Si(100). Conversely, on H-terminated Si(100), HfCl4+H2O requires 50 cycles (Tphys∼3nm) for continuous films and bulk Hf–O bonding. ...

Dual high-/spl kappa/ gate dielectric with poly gate electrode: HfSiON on nMOS and Al/sub 2/O/sub 3/ capping layer on pMOS

In this letter, a novel dual high-/spl kappa/ approach, different high-/spl kappa/ dielectrics in nMOS and pMOS, with poly Si gate electrode is introduced. By turning the Fermi-pinning effect into an advantage, this dual high-/spl kappa/ approach achieved a lower V/sub tp/ and a symmetrical V/sub tn//V/sub tp/ over a wide range of channel lengths for potential high-/spl kappa//poly Si CMOS application. In addition to the V/sub t/ control, this approach also can improve the drive current ratio between nMOS and pMOS, which would further scale the CMOS area by reducing the pMOS width.

Electrical properties of amorphous high-/spl kappa/ HfTaTiO gate dielectric with dielectric constants of 40-60

High-quality Hf-based gate dielectrics with dielectric constants of 40-60 have been demonstrated. Laminated stacks of Hf, Ta, and Ti with a thickness of /spl sim/10 /spl Aring/ each was deposited on Si followed by rapid thermal anneal. X-ray diffraction analysis showed that the crystallization temperature of the laminated dielectric stack is increased up to 900/spl deg/C. The excellent electrical properties of HfTaTiO dielectrics with TaN electrode have been demonstrated, including low interface state density (D/sub it/), leakage current, and trap density. The effect of binary and ternary laminated metals on the enhancement of dielectric constant and electrical properties has been studied.

HfTiAlO dielectric as an alternative high-k gate dielectric for the next generation of complementary metal-oxide-semiconductor devices

In this letter, the authors report on the material and electrical characterizations of high dielectric constant (k) oxide HfTiAlO for the next generation of complementary metal-oxide semiconductors. Crystallization temperature has been improved to 800–900°C versus that of HfO2. The substitution of Ti and Al in the HfO2 cubic structure results in an increased dielectric constant and an acceptable barrier height. The extracted dielectric constant is 36, and the band offset relative to the Si conduction band is 1.3eV. An equivalent oxide thickness of 11A and low leakage have been achieved with good interfacial properties.

High permittivity quaternary metal (HfTaTiOx) oxide layer as an alternative high-κ gate dielectric

The authors investigated the optical and electrical properties of the high permittivity (κ) metal oxides, HfTiO and HfTaTiO, using HfO2 as a reference and compared their material properties against their electrical performance. HfTiO has a higher κ value but its band offset is relatively smaller and, therefore, it has greater gate leakage current than HfO2. HfTaTiO has an even higher κ value which compensates for the impact of its small band offset. In addition, HfO2 was found to have more defect states than the other two films, which caused a larger hysteresis in the capacitance-voltage scan and degraded channel mobility.

Mobility enhancement of high-k gate stacks through reduced transient charging

We report a high performance NFET with a HfO/sub 2//TiN gate stack showing high field (1 MV/cm) DC mobility of 194 cm/sup 2//V-s (80% univ. SiO/sub 2/) and peak DC mobility of 239 cm/sup 2//V-s at EOT=9.5/spl Aring/. These mobility results are among the best reported for HfO/sub 2/ with sub-10 /spl Aring/ EOT and represent a potential gate dielectric solution for 45 nm CMOS technologies. A 2/spl times/ mobility improvement was realized by thinning HfO/sub 2/ from T/sub phys/=4.0 nm to 2.0 nm. The mechanism for mobility improvement is shown to be reduced transient charge trapping. Issues associated with scaling HfO/sub 2/ including film continuity, density and growth incubation are studied with low energy ion scattering (LEIS), X-ray reflectivity (XRR) and Rutherford backscattering (RBS) and indicate atomic layer deposition (ALD) HfO/sub 2/ can scale below T/sub phys/= 2.0 nm. While the mobility advancement with 2.0 nm HfO/sub 2/ is important, an additional concurrent advancement is improved V/sub t/ stability. Constant voltage stress results show /spl Delta/V/sub t/ improves 2/spl times/ after 1000s stress at 1.8V as thickness is reduced in the range 2.0-4.0 nm.

Integration issues of high-k gate stack: Process-induced charging

Electrical properties of a wide range of Hf-based gate stacks were investigated using several modifications of a standard planar CMOS process flow to address the effects of transistor processing on the electrical properties of the high-k dielectrics. Characteristics of the short channel transistors were shown to be very sensitive to the fabrication process specifics - process sequence, tools, and recipes. It was concluded that, contrary to SiO/sub 2/, the high-k films could be contaminated with reactive species during the post-gate definition fabrication steps, resulting in the formation of local charge centers. Such process-induced charging (PIC) degrades transistor performance and complicates evaluation of the intrinsic properties of high-k dielectrics. A process scheme that minimizes PIC is discussed.

Higher k HfTaTiO gate dielectric with improved material and electrical characteristics

Physical and electrical characteristics of HfTaTiO gate dielectric have been systematically investigated for the first time. HfTaTiO has a higher dielectric constant (kappa~56) and acceptable barrier height to Si (phi=1.0eV), and ultra-thin EOT(~9Aring) has been achieved. HfTaTiO dielectric shows higher crystallization temperature (900degC), reduced hysteresis, 50% higher mobility and improved Vth instability than HfO2. Moreover, HfTaTiO exhibits excellent SILC and breakdown characteristics

Improved device performance and reliability in high /spl kappa/ HfTaTiO gate dielectric with TaN gate electrode

The device performance and reliability of higher-/spl kappa/ HfTaTiO gate dielectrics have been investigated in this letter. HfTaTiO dielectrics have been reported to have a high-/spl kappa/ value of 56 and acceptable barrier height relative to Si (1.0 eV). Through process optimization, an ultrathin equivalent oxide thickness (EOT) (/spl sim/9 /spl Aring/) has been achieved. HfTaTiO nMOSFET characteristics have been studied as well. The peak mobility of HfTaTiO is 50% higher than that of HfO/sub 2/ and its high field mobility is comparable to that of HfSiON with an intentionally grown SiO/sub 2/ interface, indicative of superior quality of the interface and bulk dielectric. In addition, HfTaTiO dielectric has a reduced stress-induced leakage current (SILC) and improved breakdown voltage compared to HfO/sub 2/ dielectric.

Relationship of HfO2 Material Properties and Transistor Performance

We report on the relationship between the materials science of a HfO₂/TiN stack and transistor performance. Atomic layer deposited (ALD) HfO₂ can be scaled to a physical thickness of 1.2 nm resulting in EOT 1.0 nm. In scaling HfO₂ the interfacial SiO₂ layer (IL) is also scaled and the extent of HfO₂ crystallization is reduced. Reduced HfO₂ crystallinity is coincident with reduced threshold voltage instability (10 mV) and increased electron mobility (82% Univ. SiO ₂). For these stable, high mobility devices, we find that HfO₂ can coordinate N as Hf-N without excessive nitridation of the IL