Alvin Tian-Yi Koh

Pulsed Laser Annealing of Silicon-Carbon Source/Drain in MuGFETs for Enhanced Dopant Activation and High Substitutional Carbon Concentration

We report for the first time, the use of pulsed laser annealing (PLA) on multiple-gate field-effect transistors (MuGFETs) with silicon-carbon (Si_1-xC_x) source and drain (S/D) for enhanced dopant activation and improved strain effects. Si_1-xC_x. S/D exposed to consecutive laser irradiations demonstrated superior dopant activation with a ~60% reduction in resistivity compared to rapid thermal annealed S/D. In addition, with the application of PLA on epitaxially grown Si_0.99C_0.01 substitutional carbon concentration C_sub increased from 1.0% (as grown) to 1.21%. This is also significantly higher than the C_sub of 0.71% for rapid thermal annealed Si_0.99C_0.01 S/D. With a higher strain and enhanced dopant activation, MuGFETs with laser annealed Si_0.99C_0.01 S/D show a ~53% drain-current improvement compared to MuGFETs with rapid thermal annealed Si_0.99C_0.01 S/D.

Achieving Conduction Band-Edge Schottky Barrier Height for Arsenic-Segregated Nickel Aluminide Disilicide and Implementation in FinFETs With Ultra-Narrow Fin Widths

In this letter, we report the impact of incorporating aluminum (Al) in nickel aluminide disilcide (NiSi₂ _-xAI_x) on the Schottky-barrier for electrons (Phi_B ⁿ) in NiSi_2-xAl_x/Si contacts for parasitic series resistance reduction. A wide range of Al concentration was investigated, and an optimum value was obtained. Based on the optimum Al concentration, arsenic- segregated NiSi_2-xAl_x (As-segregated NiSi_2-xAl_x) contacts were shown to achieve conduction band-edge Schottky-barrier heights with Phi_B ⁿ = 0.133 eV. This novel As-segregated NiSi_2-xAl_x contact was integrated in FinFETs with a gate length of 80 nm and a fin width (W_Fin) of 11 nm, demonstrating improvement in current drivability of 30% over FinFETs with As-segregated NiSi contacts. We show that these ultranarrow fins (W_Fin = 11 nm) can be fully silicided reliably with NiSi_2-xAl_x, demonstrating scalability and the smallest fully silicided Si fins reported to date. For these ultra-narrow Si fins, we have successfully alleviated the concerns of parasitic series resistance without the use of selective epitaxial raised source and drain technology.

Route to Low Parasitic Resistance in MuGFETs with Silicon-Carbon Source/Drain: Integration of Novel Low Barrier Ni(M)Si:C Metal Silicides and Pulsed Laser Annealing

We report the demonstration of two distinct approaches to reduce parasitic resistances in MuGFETs with silicon-carbon (Si:C) S/D. First, the addition of dysprosium (Dy) in NiSi:C contacts reduces the electron barrier height by 38% on SiC. Device integration of the Ni(Dy)Si:C contacts provides a 30% reduction in series resistance leading to improved IDsat performance. Second, we also report the first demonstration of pulsed laser annealing (PLA) for MuGFETs with Si:C S/D for enhanced dopant activation, leading to ~50% lower series resistance. High carbon substitutional concentration (above 1.0%) in Si:C can be achieved with PLA for enhanced strain effects.

Nickel-Aluminum Alloy Silicides with High Aluminum Content for Contact Resistance Reduction and Integration in n-Channel Field-Effect Transistors

In this paper, we demonstrate the silicidation of Ni 1-x Al x alloy film with the highest Al concentration reported to date for reduced contact resistance (R con ) through process optimization. Successful formation of Ni 1-x Al x alloy silicide with the use of film that has an Al concentration as high as 51% is shown. The onset of agglomeration has been eliminated, and the silicide yields a 0.40 eV electron barrier height, which is one of the lowest reported for any nickel alloy film. Subsequently, the benefits of the film using the optimal annealing condition are further verified through an 18% saturation drive current IDsat enhancement in n-channel metal-oxide-semiconductor field-effect transistors with Ni 1-x Al x silicide compared to NiSi. In addition, this paper also elucidates the dependency of Ni 1-x Al x alloy silicide properties on Al concentration and the annealing conditions.

Source and Drain Series Resistance Reduction for N-Channel Transistors Using Solid Antimony (Sb) Segregation (SSbS) During Silicidation

We report the first integration of a novel solid antimony (Sb) segregation (SSbS) process in a transistor fabrication flow. A thin solid Sb layer, which acts as a large source of n-type dopants, was deposited beneath a metallic nickel layer prior to source-drain silicidation. Following nickel silicidation, a very high concentration of Sb was incorporated at the NiSi/Si interface. The SSbS process is demonstrated to reduce the effective Schottky barrier (SB) height and parasitic series resistance in an n-channel field-effect transistor, leading to enhanced drive current performance without degradation in the OFF -state leakage current. Performance enhancement is also maintained when the supply voltage is reduced from 1.3 to 0.8 V.

Selenium Co-implantation and segregation as a new contact technology for nanoscale SOI N-FETs featuring NiSi:C formed on silicon-carbon (Si:C) source/drain stressors

We report a novel contact technology comprising Selenium (Se) co-implantation and segregation to reduce Schottky barrier height PhiBn and contact resistance for n-FETs. Introducing Se at the silicide-semiconductor interface pins the Fermi level near the conduction band, and achieves a record low PhiBn of 0.1 eV on Si:C S/D stressors. Comparable sheet resistance and junction leakage are observed with and without Se segregation. When integrated in nanoscale SOI n-FETs with Ni-silicided Si:C S/D, the new Se-segregation contact technology achieves 36% reduction in total series resistance and 32% ION enhancement. Linear transconductance GMLin also shows large enhancement in the sample with Se-segregated contacts.

A New Salicidation Process with Solid Antimony (Sb) Segregation (SSbS) for Achieving Sub-0.1 eV Effective Schottky Barrier Height and Parasitic Series Resistance Reduction in N-Channel Transistors

We report a new CMOS-compatible salicidation process to achieve sub-0.1 eV effective Schottky barrier (SB) height for NiSi/n-Si, one of the lowest values reported-to-date, and its device integration for contact resistance reduction in n-FETs. A thin solid Antimony (Sb) layer is inserted beneath Ni prior to S/D silicidation, acting as a large source of n-type dopants. After silicidation, a very high concentration of Sb is incorporated at the NiSi/Si interface. This solid Sb segregation (SSbS) process reduces the effective SB height and parasitic series resistance. The SSbS process leads to enhanced n-FET performance without degradation in off-state leakage.