Matthew J. Rutten

High Volume Manufacturing Ramp In 90nm Dual Stress Liner Technology

The ability to meet the demand for improved microprocessor performance is made difficult due to the simultaneous need not to increase power consumption. In order to meet these conflicting demands, IBM introduced a 90 nm dual stress liner CMOS technology to improve performance without increasing power consumption (Santiago et al., 2006). In IBMs 300 mm fab, this technology was introduced on multiple microprocessors, designed by different design groups with different architectures. These microprocessors, which were originally designed for a single liner technology, were optimized for systematic yield, power/performance; circuit limited yield (CLY), and random defect limited yield. The benefit of the dual stress liner technology is demonstrated in the power/performance characteristic of a dual core microprocessor and the successful technology ramp is demonstrated by yields of two microprocessors

A study of post-chemical-mechanical polish cleaning strategies

Chemical-mechanical polishing (CMP) has emerged as the premier technique for achieving both local and global planarization. One of the primary concerns in the use of CMP, however, is the efficient and complete removal of CMP contaminants such as slurry and residual hydrocarbons. This paper discusses the removal of silica-based slurries utilized for polysilicon and oxide CMP processes. The effects of mechanical brush cleaning, chemical treatments, and polish processes on defect density for a 16 Mb memory technology are presented. In addition, the chemical compatibility of polishing slurries with various brush and polishing pad materials is discussed.