Weitao Cheng

Impact of Improved High-Performance Si(110)-Oriented Metal?Oxide?Semiconductor Field-Effect Transistors Using Accumulation-Mode Fully Depleted Silicon-on-Insulator Devices

In this study, we focus on the improved device characteristics of fully depleted silicon-on-insulator (FD-SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) on a Si(110) surface using normally off accumulation-mode device structures. It is demonstrated that the current drivability of an accumulation-mode FD-SOI n-MOSFET on Si(110) is about 1.5 times larger than that of a conventional inversion-mode FD-SOI n-MOSFET on a (110)-oriented surface. Furthermore, it is confirmed that the current drivability of an accumulation-mode FD-SOI p-MOSFET fabricated on Si(110) is also 3 times larger than that of a conventional FD-SOI pMOS formed on a Si(100) surface.

Relation Between the Mobility,

A study of the impact of the channel direction over the effective mobility and the 1/f noise in MOSFETs fabricated on (100) and (110) silicon-oriented wafers finding its outcome in the fabrication of future nonplanar device structures has been done. We found that, apart from a slight enhancement of the effective mobility maximum for the p-MOSFETs with a channel along the 100 direction, the channel direction had no effect on the noise level and performances of the transistors when they are fabricated on (100) silicon-oriented wafers. This suggests that a slight but effective enhancement of the already existing CMOS technology is possible by fabricating the MOSFETs with a channel along the 100 direction. Regarding the (110) silicon-oriented wafers, the modification of the channel direction resulted in a change of effective mobility, with the enhancement being maximum for a p-channel along the 110 direction and an n-channel along the 100 direction. Whereas this came with a noise level apparently unchanged for the p-MOSFETs, a perceptible change has been noticed for the n-MOSFETs, with the devices with a channel along the 100 direction showing the highest noise level. Finally, for the Si(110) n-MOSFETs, the earlier limitation of the effective mobility coming from the surface roughness scattering led to a negative transconductance; for the first time, it was clearly shown experimentally that two different uncorrelated noise sources generate the 1/f noise, with one becoming predominant over the other. The first noise source, attributed to the fluctuation of the insulator charge inducing fluctuations in both flatband voltage and mobility, initially contributes by itself to the total 1/f noise, then decreases and lets the second noise source, i.e., the fundamental mobility fluctuations, come out. This strongly suggests that, in the MOSFET, both noise sources, the fluctuation of the insulator charge and the fundamental mobility fluctuations subsist together, with one covering up the other according to the physical characteristics of the device and to the bias conditions.

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To reduce the surface roughness and improve the MOSFETs electric characteristics, we introduce the Si(551) surface to replace the Si(110) surface, which is very easy to roughen during the wafer cleaning processes. We experimentally demonstrate the clearly improved characteristics of being much easier to flatten on the Si(551) surface using the repeated radical oxidation technology and the strong resistance to the alkali solution for suppressing the increase in surface roughness during the wafer cleaning processes. Basic electrical characteristics of the MOSFET are improved as much by fabricating on Si(551) compared to those fabricated on the Si(110) surface. We also theoretically and experimentally demonstrate that the MOSFETs performance has clearly been improved through the introduction of the accumulation-mode (AM) silicon-on-insulator (SOI) structure. Finally, a very high performance complementary metal oxide semiconductor (CMOS) has been successfully realized on the Si(551) surface by combining the radical oxidation silicon surface flattening technology and the AM device structure.

Noise, and Channel Direction in MOSFETs Fabricated on (100) and (110) Silicon-Oriented Wafers

The investigation of the low frequency noise in p- and n-channel semiconductor-on-insulator–metal oxide semiconductor transistors fabricated on (100) and (110) silicon-oriented wafers using high advanced processes has been carried out. While for both orientations the 1∕f noise in the n-channel transistors can be explained through the ΔN formalism, the p-channel ones seem to follow the Hooge model. In addition, the new orientation presents a noise level higher than the conventional one. Furthermore, the authors showed that when there is a gap of one decade between the Si(100) and Si(110) p-channel transistors, this one has been reduced to a factor of 2 in the case of the n-channel ones. Finally, by combining the highly advanced microwave-excited high-density plasma oxidation process with the alkali-free five-step cleaning process, it has been possible to fabricate on both surfaces a very high quality oxide with a very low density of traps.

Very High Performance CMOS on Si(551) Using Radical Oxidation Technology and Accumulation-Mode SOI Device Structure

The Accumulation-Mode SOI MOSFETs, in comparison to the Inversion-Mode FD SOI MOSFETs, have several advantageous characteristics, such as higher current drivability, lower 1/f noise and suppressed kink effect, and it has been proposed that this device gives analog, digital and their mixed circuits better performances [1-3]. These advantages become larger as dopant concentration of SOI (NSOI) is increased [2,3]. However, there have been only small amount of works reported on the reliability issues in this device [4,5]. Then, this work studies the degradation mechanism of the hot carrier instability in normally-off Accumulatin-Mode SOI nMOSFETs. The schematic view of the device used in the experiment, when working in the saturation region, is shown in Fig.1. From the experimental examination of degradations in transistor transfer characteristics and flicker noise level at various transistor working region shown in Fig.2, it is revealed that the major degradation in the Accumulation-Mode nMOSFET is the positive charge and interface trap generation at the front gate Si/Insulator interface at the Drain side due to the injection of hot holes that are generated by the impact ionization caused by channel hot electrons and drained toward the front interface by the vertical electrical field in the locally depleted region as shown in Fig.3. The degradation mechanism originates from the unique current conduction mechanism in Accumulation-Mode MOSFETs in the saturation working region, that the pinch off occurs near the back Si/Insulator interface at the Drain side as schematically explained in Fig.1. It is experimentally shown that the Accumulation-Mode nMOSFETs have higher hot carrier immunity than the Inversion-Mode FD SOI nMOSFETs as shown in Fig.4. Also, the effect of the hot carrier stress to the transistor transfer characteristics such as subthreshold slope and current drivability is shown to be smaller for devices with higher dopant concentration of SOI (NSOI). It is because of the smaller influence of the front gate Si/Insulator interface to the total current drivability in higher NSOI devices in this device structure. Thus, when utilizing higher dopant concentration of SOI to this device, trade-offs do not arise between the hot carrier reliability concern and transistor performance acceleration, such as higher current drivability, smaller flicker noise level and smaller kink effect. Consequently the Accumulation-Mode MOSFET is an advantageous device structure that can suppress the effect of degradations of front gate insulator film to the transistor performance. In addition, the flicker noise analysis would be a useful tool to detect localized defects at Si/Insulator interfaces especially for devices that have multiple current conduction paths such as FinFETs, Multi-channel FETs, gate all around transistors and so on. References [1] J.Colinge, T-ED, pp.718, Vol.37, 1990 [2] W.Cheng et al., JJAP, 3110, Vol.45, 2006 [3] W.Cheng et al., to be published at ICSICT, 2006 [4] F.Duan et al., T-ED, pp.972, Vol.6, 1997 [5] A.Acovic et al., SOI Conference, pp.134, 1994 G

Different mechanism to explain the 1∕f noise in n- and p-SOI-MOS transistors fabricated on (110) and (100) silicon-oriented wafers

In this paper, a new approach to reduce the 1/f noise levels in the MOSFETs on varied silicon orientations, such as Si(100) and (110) surfaces, has been carried out. We focus on the Accumulation‐mode (AM) FD‐SOI device structure and demonstrate that the 1/f noise levels in this AM FD‐SOI MOSFETs are obviously reduced on both the Si(100) and (110) surfaces.

Hot Carrier Instability Mechanism in Accumulation-Mode Normally-off SOI nMOSFETs and Their Reliability Advantage

Introduction It is very important to improve the CMOS performance such as current drivability to satisfy the severer demand of circuits. It was reported that the mobility in the MOSFETs fabricated on flattened Si surface has been improved [1]. On the hand, it was reported that the hole mobility is much larger on Si(110) surface and the nMOSFETs performance on Si(110) have been obviously improved introducing the Accumulation-mode (AM) SOI device structure [2-3]. A very high performance CMOS can be realized on the Si(110) surface [4]. In this paper, we indicated the most effective surface flattening processes on the Si(110) and (551) surfaces to date at the first time. We experimentally demonstrated that a very high performance CMOS was successfully fabricated on Si(551) introduced the surface flattening process and AM device structure in this experiment.

Suppression of 1/f Noise in Accumulation Mode FD‐SOI MOSFETs on Si(100) and (110) Surfaces

In this work, a new MOSFETs characterization method utilizing in-wafer Kelvin contact device structure is developed. The developed method can eliminate the parasitic series resistances in MOSFETs and allows us to characterize the short channel transistor intrinsic current- voltage characteristics as well as the quantitative effects of the parasitic series resistance to the device performance, very stably and accurately. The developed analysis is useful for the characterization and parameter extractions of fabricated MOSFETs for the device/process development and optimization of ultra-thin gate insulator short channel CMOS LSIs for higher performance.

Very High Performance CMOS on Si(551) Surface using Radical Oxidation Silicon Flattening Technology and Accumulation-mode SOI Device Structure

This work reports on the modeling of the unique subthreshold characteristics of the AM-MOSFETs and the implementation to the device to control the subthreshold characteristics and electrical stress immunity. Subthreshold characteristics degradation due to hot carrier stress can be significantly suppressed by tuning the device to the bulk current controlled device. Moreover, scalability of the accumulation-mode MOSFETs becomes comparable to inversion- and intrinsic-mode MOSFETs for ultra-thin TSOI even for the deep sub-100 nm regime.

Characterization of MOSFETs intrinsic performance using in-wafer advanced Kelvin-contact device structure for high performance CMOS LSIs

Improved mobility and low flicker noise device characteristics of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are focused in this paper, using normally off accumulation mode device structures. It is demonstrated that the current drivabilities of both accumulation mode FD-SOI n-and p-MOSFETs are improved above 1.3 times compared with inversion mode MOSFETs. The effective mobilities of accumulation mode MOSFETs are improved because of the lower effective electric field at the same gate bias and the bulk current components. The flicker noise characteristics in both accumulation mode FD-SOI n- and p-MOSFETs are about 1 digit lower compared with the inversion mode MOSFETs and show the SOI layer doping concentration dependences