Ioannis Karageorgos

Implementation of templated DSA for via layer patterning at the 7nm node

In recent years major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCP). Insertion of DSA for IC fabrication is seriously considered for the 7nm node. At this node the DSA technology could alleviate costs for double patterning and limit the number of masks that would be required per layer. At imec multiple approaches for inserting DSA into the 7nm node are considered. One of the most straightforward approaches for implementation would be for via patterning through templated DSA (grapho-epitaxy), since hole patterns are readily accessible through templated hole patterning of cylindrical phase BCP materials. Here, the pre-pattern template is first patterned into a spin-on hardmask stack. After optimizing the surface properties of the template the desired hole patterns can be obtained by the BCP DSA process. For implementation of this approach to be implemented for 7nm node via patterning, not only the appropriate process flow needs to be available, but also appropriate metrology (including for pattern placement accuracy) and DSA-aware mask decomposition are required. In this paper the imec approach for 7nm node via patterning will be discussed.

Impact of interconnect multiple-patterning variability on SRAMs

The introduction of Multiple Patterning (MP) in sub-32nm technology nodes may pose severe variability problems in wire resistance and capacitance of IC circuits. In this paper we evaluate the impact of this variability on the performance of SRAM cell arrays based on the 10nm technology node, for a relevant range of process variation assumptions. The MP options we consider are the triple Litho-Etch (LE3) and the Self Aligned Double Patterning (SADP), together with Single Patterning Extreme-UV (EUV). In addition to the analysis of the worst-case variability scenario and the impact on SRAM performance, we propose an analytical formula for the estimation of SRAM read time penalty, using the RC variation of the bit line and the array size as input parameters. This formula, verified with SPICE simulations, allows a fast extraction of the statistical distribution of the read time penalty, using the Monte-Carlo method. Results on each patterning option are presented and compared.

Design strategy for integrating DSA via patterning in sub-7 nm interconnects

In recent years, major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCPs). As a result, the insertion of DSA for IC fabrication is being actively considered for the sub-7nm nodes. At these nodes the DSA technology could alleviate costs for multiple patterning and limit the number of litho masks that would be required per metal layer. One of the most straightforward approaches for DSA implementation would be for via patterning through templated DSA, where hole patterns are readily accessible through templated confinement of cylindrical phase BCP materials. Our in-house studies show that decomposition of via layers in realistic circuits below the 7nm node would require at least many multi-patterning steps (or colors), using 193nm immersion lithography. Even the use of EUV might require double patterning in these dimensions, since the minimum via distance would be smaller than EUV resolution. The grouping of vias through templated DSA can resolve local conflicts in high density areas. This way, the number of required colors can be significantly reduced. For the implementation of this approach, a DSA-aware mask decomposition is required. In this paper, our design approach for DSA via patterning in sub-7nm nodes is discussed. We propose options to expand the list of DSA-compatible via patterns (DSA letters) and we define matching cost formulas for the optimal DSA-aware layout decomposition. The flowchart of our proposed approach tool is presented.

Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits

Abstract. Major advancements in the directed self-assembly (DSA) of block copolymers have shown the technique’s strong potential for via layer patterning in advanced technology nodes. Molecular scale pattern precision along with low cost processing promotes DSA technology as a great candidate for complementing conventional photolithography. Our studies show that decomposition of via layers with 193-nm immersion lithography in realistic circuits below the 7-nm node would require a prohibitive number of multiple patterning steps. The grouping of vias through templated DSA can resolve local conflicts in high density areas, limiting the number of required masks, and thus cutting a great deal of the associated costs. A design method for DSA via patterning in sub-7-nm nodes is discussed. We present options to expand the list of usable DSA templates and we formulate cost functions and algorithms for the optimal DSA-aware via layout decomposition. The proposed method works a posteriori, after place-and-route, allowing for fast practical implementation. We tested this method on a fully routed 32-bit processor designed for sub-7 nm technology nodes. Our results demonstrate a reduction of up to four lithography masks when compared to conventional non-DSA-aware decomposition.

Density driven placement of sub-DSA resolution assistant features (SDRAFs)

In the pursuit of alternatives to traditional optical lithography, block copolymer directed self-assembly (DSA) has emerged as a low-cost, high-throughput option. However, issues of defectivity have hampered DSAs viability for large-scale patterning. Recent studies have shown copolymer fill level to be a crucial factor in defectivity, as template overfill can result in malformed DSA structures and poor LCDU after etching. For this reason, it is previously demonstrated the use of sub-DSA resolution assist features (SDRAFs) as a method of evening out template density. In this work, we propose an algorithm to place SDRAFs in random logic contact/via layouts. By adopting this SDRAF placement scheme, we can significantly improve the density unevenness and the resources used are also optimized. This is the first work to investigate the placement of SDRAFs in order to mitigate the DSA density variation problem, and it can be adopted for the mass deployment of DSA.

EUV patterned templates with grapho-epitaxy DSA at the N5/N7 logic nodes

In this paper, approaches are explored for combining EUV with DSA for via layer patterning at the N7 and N5 logic nodes. Simulations indicate opportunity for significant LCDU improvement at the N7 node without impacting the required exposure dose. A templated DSA process based on NXE:3300 exposed EUV pre-patterns has been developed and supports the simulations. The main point of improvement concerns pattern placement accuracy with this process. It is described how metrology contributes to the measured placement error numbers. Further optimization of metrology methods for determining local placement errors is required. Next, also via layer patterning at the N5 logic node is considered. On top of LCDU improvement, the combination of EUV with DSA also allows for maintaining a single mask solution at this technology node, due to the ability of the DSA process to repair merging vias. It is experimentally shown, how shaping of templates for such via multiplication helps in placement accuracy control. Peanut-shaped pre-patterns, which can be printed using EUV lithography, give significantly better placement accuracy control compared to elliptical pre-patterns.