Boon Teik Chan

A Thermally Stable and High-Performance 90-nm

In this paper, we optimize the stack of a 90-nm CMOS-friendly W\Al₂O₃\Cu conductive-bridging random access memory cell integrated in the one-transistor/one-resistor configuration. We show that the excellent Cu buffering properties of a TiW layer inserted at the Al₂O₃\Cu interface make it possible, on one hand, to ensure cell integrity after back-end-of-line processing at 400 °C and, on the other, to obtain excellent memory performances. After optimization of the Al₂O₃ layer thickness, the cell exhibits highly controlled set and reset operations, a large memory window, fast pulse programming (0 ns) at low voltage (<;3 V), and low-current (10 μA), and multilevel operation. Finally, 10⁶ cycles of write endurance lifetime with up to a three-decade memory window is demonstrated, and state stability is assessed up to 125 °C.

{\rm Al}_{2}{\rm O}_{3}\backslash{\rm Cu}

Abstract. High-defect density in thermodynamics driven directed self-assembly (DSA) flows has been a major cause of concern for a while and several questions have been raised about the relevance of DSA in high-volume manufacturing. The major questions raised in this regard are: (1) What is the intrinsic level of DSA-induced defects? (2) Can we isolate the DSA-induced defects from the other processes-induced defects? (3) How much do the DSA materials contribute to the final defectivity and can this be controlled? (4) How can we understand the root causes of the DSA-induced defects and their kinetics of annihilation? (5) Can we have block copolymer anneal durations that are compatible with standard CMOS fabrication techniques (in the range of minutes) with low-defect levels? We address these important questions and identify the issues and the level of control needed to achieve a stable DSA defect performance.

-Based 1T1R CBRAM Cell

In this paper we demonstrate excellent memory performances of a 90nm CMOS-friendly W\Al2O3\TiW\Cu CBRAM cell integrated in a 1T1R configuration and withstanding the back-end of line thermal budget of 400°C. The cell exhibits low-power and highly controlled set and reset operations, allowing reversible multilevel programming controlled by both the set current and the reset voltage. Low-voltage (<;3V) operation is obtained down to 10ns-long write pulse both for set and reset, and allowing >106 write endurance with a 2-decade memory window. State stability is assessed up to 125°C. Moreover, due to low slope of the voltage-log(time) relationship the cell also shows excellent voltage-disturb immunity assessed up to +/-0.5V and extrapolated to 10 years.

Defect mitigation and root cause studies in 14 nm half-pitch chemo-epitaxy directed self-assembly LiNe flow

A graphoepitaxy directed self-assembly process using cylindrical phase block copolymers is regarded as a promising approach for patterning irregularly distributed contact holes in future integrated circuits. However, control over cylinder profile and open hole rate, among others, needs to be proven before this technique can be implemented in device fabrication. Computational simulation studies predict that selective control over the surface energy of the template bottom and sidewall is crucial for achieving perpendicular cylinders in an adequate range of template dimensions and block copolymer fill levels. This work offers an experimental investigation of the influence of the surface energy on the morphology of the assembly inside the template. For this study, a dedicated surface energy modification is implemented in our process flow. Selective control over the surface energy of the template bottom and sidewall is achieved by using random copolymer brushes. The optimization of surface energy prior to the ...

90nm W\Al 2 O 3 \TiW\Cu 1T1R CBRAM cell showing low-power, fast and disturb-free operation

Surface texturing is an imperative process to reduce the reflection of the incident light on solar cells, by enhancing sunlight diffusion into the silicon solar cells for photon generation. As a result, the current generation can be increased. In this study, the plasma texturing process with linear microwave plasma sources has been benchmarked with the industrial acidic iso-texturing process on 156×156 mm2 multicrystalline substrates. By optimizing the plasma texturing parameters, the absolute solar cells efficiency can be increased by 4.9% for 150 µm thickness silicon substrate. The proposed process offers a significant advantage over the standard acidic iso-texturing without major modification in the existing industrial solar cells manufacturing sequence. In order to explain plasma-induced surface morphology changes, the Kardar–Parisi–Zhang (KPZ), Petri–Brault, and Jason–Drotar models are used.

Implementation of surface energy modification in graphoepitaxy directed self-assembly for hole multiplication

Surface texturing of crystalline silicon solar cells allows reduction of the reflection of sunlight and enhances photon generation. Plasma-based texturing offers significant advantages over the conventional wet approach, i.e., reduced Si consumption, thin wafer compatibility, increased throughput, and reduced chemical waste. However, it still suffers from insufficient electric yield, i.e., bad performance of plasma-processed solar cells. This paper describes advances made in plasma texturing by means of a linear microwave plasma source. The advantage of a two-step plasma-texturing process is demonstrated, leading to a smoother surface roughness, and resulting in an increased open-circuit voltage, together with a reduced processing time. In addition, the described technology allows a significant reduction of surface damage and could be implemented on a production line for crystalline silicon solar cell manufacturing.

Study of SF6/N2O Microwave Plasma for Surface Texturing of Multicrystalline (<150 µm) Solar Substrates

In the past few years the quality of Edge-defined Film-fed Growth (EFG) material has strongly improved and can now compete with most standard multicrystalline materials. The maximum conversion efficiency of solar cells based on high quality EFG material is at the moment mostly limited by the applied solar cell processing steps. The state-of-the-art high efficiency process at the University of Konstanz (UKN) in combination with some additional processing steps is presented. The latter include hydrogen passivation of bulk defects, texturisation of the front surface by remote SF6 plasma (most samples shown here were textured at IMEC), surface passivation using a silicon oxide / silicon nitride stack and the application of Laser Fired Contacts (LFC). Single additional processing steps are investigated as well as various combinations of additional processing steps.

Two-Step Plasma-Texturing Process for Multicrystalline Silicon Solar Cells With Linear Microwave Plasma Sources

Polyphthalaldehyde is a self-developing resist material for electron beam and thermal scanning probe lithography (t-SPL). Removing the resist in situ (during the lithography process itself) simplifies processing and enables direct pattern inspection, however, at the price of a low etch resistance of the resist. To convert the material into a etch resistant hard mask, we study the selective cyclic infiltration of trimethyl-aluminum (TMA)/water into polyphthalaldehyde. It is found that TMA diffuses homogeneously through the resist, leading to material expansion and formation of aluminum oxide concurrent to the exposure to water and the degradation of the polyphthalaldehyde polymer. The plasma etch resistance of the infiltrated resist is significantly improved, as well as its stability. Using a silicon substrate coated with 13 nm silicon nitride and 7 nm cross-linked polystyrene, high resolution polyphthalaldehyde patterning is performed using t-SPL. After TMA/H2O infiltration, it is demonstrated that pattern transfer into silicon can be achieved with good fidelity for structures as small as 10 nm, enabling >10× amplification and low surface roughness. The presented results demonstrate a simplified use of polyphthalaldehyde resist, targeting feature scales at nanometer range, and suggest that trimethyl-aluminum infiltration can be applied to other resist-based lithography techniques.

Advanced processing steps for high efficiency solar cells based on EFG material

For further reduction of the crystalline Silicon solar cell cost/Wp, a dual approach is required: Further reduction of the silicon material by using thinner wafer and further increasing the conversion efficiency. Considering wafer thicknesses of 150µm and below the standard process with Ag screen-printed contacts on 50–60Ω/sq emitter and full Al BSF cannot provide the necessary efficiency increase. The reason for that is the increasing influence of the rear surface recombination current, which becomes a limited current loss mechanism. Within the Photovoltaic department in IMEC a research program has been launched with the goal of providing industrial processes for the next generation thin crystalline silicon solar cells. In this paper we are reporting on the development of a process toolbox that allows overcoming the full Al-BSF and the Ag-screen printing front-side metallization limitations. The next step towards higher efficiency targets is the implementation of novel emitter schemes and consequently advanced front-side metallization like electro-plating of copper for further photocurrent and fillfactor increase. By implementing Cu-plating as a front-side metallization, large area cells with efficiencies up to 18.4% have been fabricated. These are the initial steps for a cell concept that potentially can reach 19% efficiency in an industrial process flow. The progress towards an industrial Passivated Emitter and Rear Locally doped cell concept (i-PERL) is presented.

Conversion of a Patterned Organic Resist Into a High Performance Inorganic Hard Mask for High Resolution Pattern Transfer.

When considering the cost of a photovoltaic module, still a large part consists of silicon wafer material. One solution is the usage of ribbon material, which provides moderate quality material at a low cost due to low kerf losses. Here we present the use of Ribbon on a Sacrificial Template (RST) wafers in a classic solar cell process. The quality of this material is determined by Quasi Steady State Photo Conductance (QSSPC) lifetime measurements indicating a minority carrier diffusion length up to 100µm. The classic solar cell processing combining various metallization techniques like screenprinting and evaporation leads to energy conversion efficiencies up to 11.5% on 11.44cm2 large ribbons. A big boost in efficiency is related to the use of plasma texturing, developed at IMEC, which proofs to be a good technique for texturing poly-crystalline material. The results presented in this paper show that RST material can become a cost competitive ribbon technology for solar cell applications.