J. Bucchignano

Simple fabrication scheme for sub-10 nm electrode gaps using electron-beam lithography

An innovative and simple method, based on electron-beam (e-beam) overlapping and overexposure techniques, is developed to fabricate sub-10 nm electrode gaps with very good electrical properties. Gaps with 4 to 10 nm spacing can be fabricated using a proper e-beam dose and pattern-developing time. The fabrication yield is nearly 100% for 8–9 nm gaps, but significantly smaller for 3–4 nm gaps. The gap leakage resistance is around 1012–1013u2009Ω, implying very good isolation. As an example, we present a transport study on a single 8 nm Co particle junction using a 10 nm gap.

In situ x‐ray diffraction analysis of the C49–C54 titanium silicide phase transformation in narrow lines

The transformation of titanium silicide from the C49 to the C54 structure was studied using x‐ray diffraction of samples containing arrays of narrow lines of preformed C49 TiSi2. Using a synchrotron x‐ray source, diffraction patterns were collected at 1.5–2u2009°C intervals during sample heating at rates of 3 or 20u2009°C/s to temperatures of 1000–1100u2009°C. The results show a monotonic increase in the C54 transition temperature by as much as 180u2009°C with a decreasing linewidth from 1.0 to 0.1 μm. Also observed is a monotonic increase in (040) preferred orientation of the C54 phase with decreasing linewidth. The results demonstrate the power of in situ x‐ray diffraction of narrow line arrays as a tool to study finite size effects in thin‐film reactions.

Graphene radio frequency devices on flexible substrate

Graphene is a very promising candidate for applications in flexible electronics due to its high carrier mobility and mechanical flexibility. In this paper, we present results on graphene RF devices fabricated on polyimide substrates with cutoff frequencies as high as 10u2009GHz. Excellent channel mobility and current saturation are observed in graphene long channel devices on polyimide. Graphene devices on polyimide also show very good temperature stability from 4.4u2009K to 400u2009K and excellent mechanical flexibility up to a bending radius of 1u2009mm. These demonstrated properties make graphene an excellent candidate for flexible wireless applications.

An ultra-low power 0.1 /spl mu/m CMOS

Ultra-low power operation of 0.1 /spl mu/m CMOS is demonstrated at power supply voltages well below 1 V. Design trade-offs among gate delay, active power, and standby power are carried out in a power supply-threshold voltage design space. Experimental results show a ring oscillator delay of 106 ps at a power supply voltage of 0.5 V, and a minimum power-delay product of 0.03 fJ/stage (switching factor=0.01) at 0.4 V. A 20X reduction in power/circuit is achieved at the same performance level as 0.25 /spl mu/m CMOS.<<ETX>>

Sub-30 nm pitch line-space patterning of semiconductor and dielectric materials using directed self-assembly

The authors demonstrate pattern transfer of 29-nm-pitch self-assembled line-space polystyrene-poly(methyl methacrylate) patterns generated by graphoepitaxy into three important materials for semiconductor device integration: silicon, silicon nitride, and silicon oxide. High fidelity plasma etch transfer with production-style reactors was achieved through co-optimization of multilayer masking film stacks and reactor conditions. The authors present a systematic study of the line edge roughness (LER) and line width roughness evolution during pattern transfer. Application of a postetch annealing process shows reduction of the LER of silicon features from around ∼3u2009nm to less than 1.5u2009nm. These results further demonstrate that directed self-assembly-based patterning may be a suitable technique for semiconductor device manufacturing.

Sub-50nm half-pitch imaging with a low activation energy chemically amplified photoresist

Critical lithographic dimensions are rapidly approaching the sub-50nm regime where there is a concern that image blur due to acid diffusion will impose a practical limit to the resolution of chemically amplified (CA) resists. Although recent EUV and 193- and 157nm immersion interferometric experiments have reportedly resolved line-space arrays with individual dimensions on the order of ∼40nm, smaller nested features are likely to prove problematic. Numerous reports suggest that conventional photoresist performance degrades rapidly at half-pitch dimensions in this range. New approaches to processing and materials development of photoresists will likely be required if the concept of chemical amplification is to be extended to the 32nm node and beyond. In this article we show that through materials choice and proper processing, image blur can be controlled to an extent where dense features below 40nm can routinely be resolved in CA resists. We describe our studies on high-sensitivity resists of differing act...

Looking into the crystal ball: future device learning using hybrid e-beam and optical lithography (Keynote Paper)

Semiconductor process development teams are faced with increasing process and integration complexity while the time between lithographic capability and volume production has remained more or less constant over the last decade. Lithography tools have often gated the volume checkpoint of a new device node on the ITRS roadmap. The processes have to be redeveloped after the tooling capability for the new groundrule is obtained since straight scaling is no longer sufficient. In certain cases the time window that the process development teams have is actually decreasing. In the extreme, some forecasts are showing that by the time the 45nm technology node is scheduled for volume production, the tooling vendors will just begin shipping the tools required for this technology node. To address this time pressure, IBM has implemented a hybrid-lithography strategy that marries the advantages of optical lithography (high throughput) with electron beam direct write lithography (high resolution and alignment capability). This hybrid-lithography scheme allows for the timely development of semiconductor processes for the 32nm node, and beyond. In this paper we will describe how hybrid lithography has enabled early process integration and device learning and how IBM applied e-beam & optical hybrid lithography to create the worlds smallest working SRAM cell.

Resist contrast enhancement in high resolution electron beam lithography

While lithography tooling continues to advance to achieve the resolution and overlay requirements of most advanced devices, resist science, and technology proceed with material advancements and process enhancements to ultimately achieve the sensitivity and contrast required. In this paper, we report approaches of modifying a single layer resist system to achieve the characteristics of a bilayer resist system without the complexity of a multilayer process.The top surface of the single layer resist is made less sensitive to electron beam exposure and development effects. One of the methods used consists of desensitizing the top surface of a positive resist which operates on the chemical amplification principle, prior to exposure. The desensitization step is achieved by controlling the post‐apply bake condition during resist film preparation. Proper bake control of this resist provides the exposed regions with an initial dissolution rate which is three times slower than that in the resist bulk. This surface ...

Hydrogen silsesquioxane-based hybrid electron beam and optical lithography for high density circuit prototyping

The authors report on a hybrid lithography process that integrates electron beam lithography (EBL) and optical photolithography. To maximize resolution and density, the EBL exposure is performed using a hydrogen silsesquioxane-based resist, while the photolithographic exposure is performed using standard positive or negative tone 248nm photoresists. Both exposures take place on a common underlayer consisting of an antireflective coating (ARC). During pattern transfer into the ARC layer, a composite image of the two lithographic exposures is formed creating a robust and versatile etch mask for further pattern transfer into the substrate. They demonstrate the utility of this technique by using it to pattern the active, gate, and wiring levels of complementary metal oxide semiconductor devices and circuits consisting of trigated Fin-based field effect transistors. These devices have a minimum active area pitch of 50nm, minimum gate pitch of 90nm, and achieve densities suitable for 15nm node static random acc...

Pattern transfer of directed self-assembly (DSA) patterns for CMOS device applications

We present a study on the optimization of etch transfer processes for circuit relevant patterning in the sub 30 nm pitch regime using directed self assembly (DSA) line-space patterning. This work is focused on issues that impact the patterning of thin silicon fins and gate stack materials. Plasma power, chuck temperature and end point strategy is discussed in terms of their effect on critical dimension (CD) control and pattern fidelity. A systematic study of post-plasma etch annealing processes shows that both CD and line edge roughness (LER) in crystalline Si features can be further reduced while maintaining a suitable geometry for scaled FinFET devices. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode and a SiN capping layer are also presented. We conclude with the presentation of a strategy for realizing circuit patterns from groups of DSA patterned fins. These combined results further establish the viability of DSA pattern generation as a potential method for CMOS integrated circuit patterning beyond the 10 nm node.