J. Urresti

Analysis of hot-carrier degradation in a SOI LDMOS transistor with a steep retrograde drift doping profile

This paper reports the electrical performances of a RF SOI power LDMOS transistor with a retrograde doping profile in the entire drift region. A comparison between retrograde and conventional uniformly doped drift SOI power LDMOS transistors is provide by means of a numerical simulation analysis. The proposed structures exhibit better performances in terms of trapped electron distribution and transconductance degradation with no modification of the breakdown voltage capability. Simulation results show that, at a given bias conditions, the reduction of lateral electric field peak at the silicon surface due to the implementation of the retrograde doping profile accounts for the observed reduction of the hot carrier degradation effect.

Lateral punch-through TVS devices for on-chip protection in low-voltage applications

A novel lateral punch-through TVS (Transient Voltage Suppressor) structure addressed to on-chip protection in very low voltage applications is reported in this paper. Different lateral TVS structures have been studied in order to optimize the electrical performances related with the surge protection capability. Lateral TVS structures with a four-layer doping profile exhibit the best electrical performances, as in the case of vertical TVS devices. The dependence of the basic electrical characteristics on the technological and geometrical parameters is also analysed. Finally, the electrical performances of lateral TVS structures are compared with those of vertical punch-through TVS devices and conventional Zener diodes, being the leakage current level reduced two orders of magnitude in the case of the lateral architecture. Lateral TVS structures exhibits similar performance than vertical counterparts with the advantage of easiest on-chip integration.

Efficiency of SOI-like structures for reducing the thermal resistance in thin-film SOI power LDMOSFETs

Silicon-on-insulator (SOI)-like structures to remove the heat from the active silicon layer in thin-film SOI power lateral double diffused MOS field-effect transistors have been recently reported. This paper provides an experimental demonstration of their efficiency. For this purpose, a heater-sensor system based on poly-Si and platinum resistor stripes, respectively, has been integrated in thermal contact with the active silicon layer under study. The thermal resistance reduction due to the contact-through-buried-oxide technique and the SOI-multilayer substrates have been analyzed at steady state using different SOI layer thicknesses and heat source lengths, in accordance with the state-of-the-art. In addition, experimental results are supported by those extracted from numerical simulation of the heater-sensor system.

Optimisation of very low voltage TVS protection devices

Abstract This paper is aimed at the design and optimisation of advanced Transient Voltage Suppressors (TVS) devices for IC protection against ESD. A four-layer N+P+PN+ structure has been used to achieve breakdown voltages lower than 3 V. The effect of the critical geometrical and technological parameters on the TVS electrical characteristics is analysed with the aid of technological and electrical simulations. In this sense, the trade-off between voltage capability, leakage current and clamping voltage has been optimised. Fabricated TVS devices exhibit better electrical performances than those of the equivalent three-layer TVS device counterparts.

Low voltage TVS devices: design and fabrication

This paper addresses the optimisation of advanced transient voltage suppressor (TVS) devices for integrated circuit (IC) protection against electrostatic discharge (ESD) by means of technological and electrical simulations. An N/sup +/PP/sup +/N/sup +/ bipolar technology for low voltage (less than 3.3 V) TVs has been designed by optimising the trade-off between voltage capability and leakage current.

Analysis and optimization of safe-operating-area of LUDMOS transistors based on 0.18 µm SOI CMOS technology

This paper is focused on the design and optimization of power LDMOS transistors (VBR > 120 V) with the purpose of integrating them with a new generation of smart-power technology based upon 0.18 µm SOI-CMOS technology. Different LDMOS design structures with optimal /VBR trade-off have been analyzed in order to compare their electrical safe-operating-area (SOA). The influence of some important design parameters such as the STI length (LSTI) and technological concerns such as the P-well and N-well mask position distance is also exhaustively analyzed in this work.

Degradation analysis in SOI LDMOS transistors with steep retrograde doping profile and source field plate

The benefits of implementing a source field plate in RF ultra-thin SOI power LDMOS transistors with a retrograde doping profile in the entire drift region is evaluated in this paper in terms of hot-carrier degradation (HCD) and capacitance behaviour. The optimisation of the retrograde doping profile allows the current path to be diverted deep inside the active silicon layer in such a way that the surface damage originated by hot carriers is attenuated. However, a slight change in the dose implanted into the drift region can deteriorate the performance in terms of HCD and capacitance. Among the well-known benefits, such as better power efficiency and higher reliability, simulation results show that the source field plate (SFP) leads to an improvement of device stability to implanted dose fluctuations in LDMOS transistors with retrograde doping profiles. Moreover, the retrograde doping profile along with the SFP helps to accelerate the depletion process in the drift region, increasing the variation of the gate-drain capacitance (C/sub gd/) as a function of the drain voltage and thus improving the RF performance.

Study of layout influence on ruggedness of NPT-IGBT devices by physical modelling

Abstract During clamped inductive turn-off, the electro-thermal mismatch introduced by the layout of NPT-IGBT devices could significantly enhance the risk of failure, thus reducing the lifetime of power inverters. A TCAD simulation strategy that takes into account the layout influence on the NPT-IGBT devices’ ruggedness has been performed by splitting the dies into three individual structures considering: the core inner cells, core outer cells with the edge termination, and core outer cells with the edge termination and the gate runner. Thus, the electro-thermal mismatch due to the periphery symmetry itself is taken into account. Simulation results support that the failure is due to the symmetry break down introduced by the gate runner and edge termination presence.

Lateral Punch-Through TVS Devices: Design and Fabrication

The design and fabrication of a novel lateral punch-through TVS (Transient Voltage Suppressor) device addressed to on chip protection against ESD (ElectroStatic Discharge) is reported in this paper. In order to reduce the breakdown voltage, the inclusion of a field place, connected to the collector, has been proposed for first time. The compatible CMOS technological process followed in the integration of this device and its technological and electrical characterization is large explained, being these results in agreement with the previous studies.

An analytical model to predict the short-circuit thermal failure in SOI LDMOS with Linear Doping Profile

The heat generation process inside LDMOS structures accounting for Linear Doping Profile (LDP) or Variation on Lateral Doping (VLD) is analysed in this paper by means of numerical simulation tools and analytical modeling. A uniform heat density, mainly due to the Joule effect, has been demonstrated to be generated in a rectangular shaped heat source, contained in the drift region. The dimensions of such a heat source are dependent on the drain bias as well as on the geometrical /technological structure parameters. Accordingly, we have developed an analytical electro-thermal model to provide physical insight into the heat generation process, arid to predict dynamic temperature distribution by means of heat flow equation approach. The model is suitable for typical high gate bias operation; i.e., when the power dissipation in the drift region is predominant respect to the channel region one.