Jacob Murray

Design Space Exploration for Wireless NoCs Incorporating Irregular Network Routing

The millimeter-wave small-world wireless network-on-chip (mSWNoC) is an enabling interconnect architecture to design high-performance and low-power multicore chips. As the mSWNoC has an overall irregular topology, it is essential to design and optimize suitable deadlock-free routing mechanisms for it. In this paper, we quantify the latency, energy dissipation, and thermal profiles of mSWNoC architectures by incorporating irregular network routing strategies. We demonstrate that the latency, energy dissipation, and thermal profile are affected by the adopted routing methodologies. The overall system performance and thermal profile are governed by the traffic-dependent optimization of the routing methods. Our aim is to establish the energy-thermal-performance trade-offs for the mSWNoC depending on the exact routing strategy and the characteristics of the benchmarks considered.

Energy-efficient multicore chip design through cross-layer approach

Traditional multi-core designs, based on the Network-on-Chip (NoC) paradigm, suffer from high latency and power dissipation as the system size scales up due to the inherent multi-hop nature of communication. Introducing long-range, low power, and high-bandwidth, single-hop links between far apart cores can significantly enhance the performance of NoC fabrics. In this paper, we propose design of a small-world network based NoC architecture with on-chip millimeter (mm)-wave wireless links. The millimeter wave small-world NoC (mSWNoC) is capable of improving the overall latency and energy dissipation characteristics compared to the conventional mesh-based counterpart. The mSWNoC helps in improving the energy dissipation, and hence the thermal profile, even further in presence of network-level dynamic voltage and frequency scaling (DVFS) without incurring any additional latency penalty.

Performance evaluation of wireless NoCs in presence of irregular network routing strategies

The millimeter (mm)-wave small-world wireless NoC (mSWNoC) is an enabling interconnect architecture to design high performance and low power multicore chips. As the mSWNoC has an overall irregular topology, it is extremely important to design suitable deadlock-free routing mechanisms for it. In this paper we quantify the latency, energy dissipation, and thermal profiles of mSWNoC architectures by incorporating irregular network routing strategies. We demonstrate that the latency, energy dissipation, and thermal profile are affected by the adopted routing methodologies. In presence of the benchmarks considered, the variation in latency and energy dissipation is small. However, the network hotspot temperature can vary considerably depending on the exact routing strategy and the characteristics of the benchmark.

DVFS-enabled sustainable wireless NoC architecture

In the design of high-performance massive multi-core chips, power and heat have become dominant constraints. Increased power consumption can raise chip temperature, which in turn can decrease chip reliability and performance and increase cooling costs. In this paper we demonstrate how small-world Network-on-Chip (NoC) architectures with long-range wireless links and DVFS-enabled wireline links facilitate design of energy and thermally efficient and hence sustainable multi-core chips. Our performance analysis demonstrates that the DVFS-enabled Wireless NoC improves overall energy dissipation by around 60% and reduces the temperature of the hottest node in the network by up to 30% depending on the specific application without incurring any latency penalty over a traditional mesh network.

DVFS Pruning for Wireless NoC Architectures

The millimeter wave small world network on a chip is an emerging paradigm to design low power and high-bandwidth massive multicore chips. By reducing the hop count between largely separated communicating cores, wireless shortcuts in mSWNoC have been shown to carry a significant amount of the overall traffic within the network. The amount of traffic detoured in this way is substantial and the low power wireless links enable energy savings [1]. The overall energy dissipation and thermal profile of the mSWNoC can be improved even further if the characteristics of the wireline links and associated switches are optimized according to the traffic patterns. Dynamic voltage and frequency scaling (DVFS) is a popularmethodology to optimize the power usage/heat dissipation of electronic systems without significantly compromising overall system performance.We have already demonstrated that DVFS enables improvement of power and thermal profiles of mSWNoC-enabled multicore chips.

Iterative detection and decoding for the four-rectangular-grain TDMR model

This paper considers detection and error control coding for the two-dimensional magnetic recording (TDMR) channel modeled by the two-dimensional (2D) four-rectangular-grain model proposed by Kavcic, Huang et. al. in 2010. This simple model captures the effects of different 2D grain sizes and shapes, as well as the TDMR grain overwrite effect: grains large enough to be written by successive bits retain the polarity of only the last bit written. We construct a row-by-row BCJR detection algorithm that considers outputs from two rows at a time over two adjacent columns, thereby enabling consideration of more grain and data states than previously proposed algorithms that scan only one row at a time. The proposed algorithm employs soft-decision feedback of grain states from previous rows to aid the estimation of current data bits and grain states. Simulation results using the same average coded bit density and serially concatenated convolutional code (SCCC) as a previous paper by Pan, Ryan, et. al. show gains in user bits/grain of up to 6.7% over the previous work when no iteration is performed between the TDMR BCJR and the SCCC, and gains of up to 13.4% when the detector and the decoder iteratively exchange soft information.

Sustainable dual-level DVFS-enabled NoC with on-chip wireless links

Wireless Network-on-Chip (WiNoC) has emerged as an enabling technology to design low power and high bandwidth massive multi-core chips. The performance advantages mainly stem from using the wireless links as long-range shortcuts between far apart cores. This performance gain can be enhanced further if the characteristics of the wireline links and the processing cores of the WiNoC are optimized according to the traffic patterns and workloads. In this work, we demonstrate that by incorporating both processor- and network-level dynamic voltage and frequency scaling (DVFS) in a WiNoC, the power and thermal profiles can be enhanced without a significant impact on the overall execution time. We also show that depending on the benchmark applications, temperature hotspots can be formed either in the processing core or in the network infrastructure. The proposed dual-level DVFS is capable of addressing both.

Iterative Detection and Decoding for TDMR With 2-D Intersymbol Interference Using the Four-Rectangular-Grain Model

This paper considers detection and error control coding for the 2-D magnetic recording (TDMR) channel modeled with the 2-D four-rectangular-grain model (FRGM). This simple model captures the effects of different 2-D grain sizes and shapes, as well as the TDMR grain overwrite effect. We construct a row-by-row Bahl-Cocke-Jelinek-Raviv-based detector that processes two rows at a time. Simulation results using the same coded bit density and channel code as a previous paper on FRGM detection show gains in user bits per grain of up to 13.4% when the detector and the decoder iteratively exchange soft information, resulting in densities higher than 0.5 user bits per grain under all scenarios simulated. When the proposed detector/decoder operates on coded bits read from a random Voronoi grain model, the achieved density drops to 0.25 user bits per grain due to model mismatch between the detector and the data. Finally, this paper considers an iterative detection and decoding scheme combining TDMR detection, 2-D-intersymbol interference (ISI) detection, and soft-in/soft-out channel decoding in a structure with two iteration loops. Simulation results for the concatenated FRGM and

Performance Evaluation of Congestion-Aware Routing with DVFS on a Millimeter-Wave Small-World Wireless NoC

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Dual-Level DVFS-Enabled Millimeter-Wave Wireless NoC Architectures

averaging mask ISI channel with 10 dB signal-to-noise ratio show that densities of 0.496 user bits per grain and above can be achieved over the entire range of FRGM grain probabilities.