Jade M. Kizer

Pseudo-differential signaling scheme based on 4b/6b multiwire code

The majority of todaypsilas memory interfaces use single-ended signaling instead of differential signaling. Extending the performance of single-ended systems beyond a few Gb/s is a very challenging task mainly due to crosstalk and SSO noise. This paper presents a pseudo-differential signaling scheme based on an encoding technique which maps 4 bits of data to six coded bits with balanced numbers of 0s and 1s. The proposed scheme successfully removes the impact of SSO and VREF noise. The simulation results based on graphics memory channels show significant improvements in performance over the non-coded case.

Equalization of mid-frequency power supply noise via a spectrum-shaping encoder for parallel buses

Noise from the simultaneous switching of outputs (SSO) creates a significant problem for high-speed parallel buses that use single-ended signaling. Further exacerbating this problem is the fact that many single-ended interfaces share the return path of numerous signals with the same power delivery network (PDN) used to power the I/O transceiver circuitry. These single-ended interfaces share power and ground conductors in an effort to reduce the cost associated with package pin count and chip pad area. In addition to creating low-cost interfaces, there is a need for performance enhancing techniques that are “interface compatible”, which helps to ease their adoption. This paper introduces a new concept in bus coding that shapes the spectrum of aggregate bus current in an effort to “equalize” the induced voltage response of a power supply. The single-ended buses discussed in this paper are those used in the industry standard interfaces of todays graphics systems, and possibly the interfaces that may be used in future generations of main memory.

System-level BER test and jitter extraction of a 6.4Gbps parallel chip to chip bus on the first generation CELL/spl trade/ processor

At multi-gigahertz data rate, it is a very challenging task to have an accurate and reliable method to measure system performance, in particular, to account for the impact of both deterministic and random jitter. Such measurement method must be able to capture major jitter components without the need of long testing time as well as expensive testing hardware. In this paper, we extend our previous work (Madden, 2004) to extract system level jitter in terms of deterministic and random jitter and extrapolate to very low bit error rate for a 6.4Gbps parallel bus. To that end, we designed an error counter and a bit counter into our FlexIO/spl trade/ interface so that built-in self-test can be performed without the need for a bit error rate tester (BERT). In addition, all I/Os of the interface can be tested simultaneously. Finally, we demonstrate the accuracy of the proposed method by correlating with traditional direct jitter measurement method.

Characterization and hardware correlation of multi-gigahertz parallel bus with transmit pre-emphasis equalization

This work describes the characterization and hardware correlation of an equalized parallel bus for multi-gigahertz data-rate operation. In contrast to our earlier paper where interconnect design, modeling, and equalization of band-limited channels were discussed, This work focuses on characterization and correlation methodologies of complete passive and active chip-to-chip communication systems. The simulation and measurement results of equalized channels are correlated in both time and frequency domains. The performance of equalized channels is also verified by comparing the measured and simulated eye diagrams for various values of equalization coefficients up to 8 GHz data rates.