James D. Gallia

A trench transistor cross-point DRAM cell

A 1T DRAM cell with both the transistor and the capacitor fabricated on the sidewalls of a deep trench is described. Trench Transistor Cell (TTC) fabrication and characterization are discussed.

Trench transistor DRAM cell

A new one-transistor DRAM cell with both the transistor and the capacitor fabricated on the trench sidewalls is described. With the signal stored on the polysilicon node surrounded by oxide, the cell is expected to have a high alpha particle immunity. The cell occupies only 9 µm2using 1-µm design rules. This cell size is sufficiently small to enable a 4-Mbit DRAM of reasonable chip size with these design rules, and possesses further scalability for 16-Mbit DRAMs.

BiCMOS ASIC for high performance systems

The advantages of BiCMOS technology are discussed and illustrated by comparing the delay of BiCMOS and CMOS gates. High-speed fully static conditional-sum addition (CSA) logic adders designed using a 1-b CSA adder, a two-to-one multiplexer, and a BiCMOS inverter are described. The high drive capability of BICMOS minimizes the speed and area penalties that occur in longer word-length CSA adders using CMOS buffers. The significant performance improvement of BiCMOS over CMOS for dense-memory designs (especially in the word-line driver and sense-amp sections) is also discussed. The speed and high drive capability of BiCMOS logic is well suited to reducing the word-line delay, which can constitute 50-60% of the access time delay of large memory designs. Access time of memory blocks is also reduced by using bipolar sensing. The BiCMOS sense amp provides the ability to quickly sense small transitions on highly capacitive bit lines within large memory arrays. A 64-tap fixed coefficient FIR (finite impulse response) digital filter for a video image application designed using this gate array is examined.<<ETX>>