S. Van Huylenbroeck

Towards THz SiGe HBTs

This paper summarizes the technological developments carried out on SiGe HBTs in the frame of the European project DOTFIVE. The architectures of the different partners and their performances are presented and discussed showing that the project objectives have been met.

Investigation of PECVD dielectrics for nondispersive metal-insulator-metal capacitors

Metal-insulator-metal (MIM) capacitors with PECVD nitride exhibit trap-induced dispersive behavior, which leads to degradation in capacitor linearity at low frequencies, limiting the accuracy in precision analog circuits. While LPCVD oxide results in nondispersive behavior, the high deposition temperature excludes the use of LPCVD dielectrics for MIM capacitors using the standard back-end metal layers as capacitor bottom plates. The latter is preferred in view of the low substrate coupling needed for RF applications. In this work, alternative PECVD dielectrics have been investigated with respect to frequency dependence of voltage linearity, hysteresis, matching, and leakage characteristics. It will be shown that ONO stacks offer a combination of good voltage linearity, absence of dispersive behavior and hysteresis, excellent matching, and low leakage.

Advanced process modules and architectures for half-terahertz SiGe:C HBTs

The European project DOTFIVE [1] addresses evolutionary scaling of self-aligned selective epitaxial base SiGe:C HBTs, investigates novel SiGe:C HBT architectures, and develops novel process modules to push SiGe BiCMOS towards 500 GHz Fmax and 2.5 ps gate delay. In this paper, scaling issues of SiGe:C HBT technology will be addressed. The limitations of the different commonly used architectures will be described, and measures taken in the project to overcome these limitations will be summarized. Initial results indicate that the objectives of the project can be reached.

A Novel Fully Self-Aligned SiGe:C HBT Architecture Featuring a Single-Step Epitaxial Collector-Base Process

In this paper we describe a novel fully self-aligned HBT architecture, which enables a maximum reduction of device parasitics. TCAD simulations show that this architecture is capable of achieving fT/fmax values of 295/425 GHz for an effective emitter area of 0.13times5 mum2. In this new process approach, which is fully CMOS compatible, the collector and base are grown in a single-step non-selective epitaxial process on top of pre-defined bipolar areas. This provides new opportunities for collector-base profile engineering. The collector drift region and the extrinsic base are made self-aligned to the emitter by means of a dry etch that removes all polycrystalline material. The remaining epitaxial pedestal defines the intrinsic device and makes deep trench isolation redundant. We describe the major features of the integration scheme and show measured fT/fmax values of 300/220 GHz on the first fabricated devices with an effective emitter area of 0.13times5 mum2.

A 0.35 /spl mu/m SiGe BiCMOS process featuring a 80 GHz f/sub max/ HBT and integrated high-Q RF passive components

A SiGe HBT, fabricated by means of selective epitaxy, and high-Q RF passive components have been integrated into a 0.35 /spl mu/m BiCMOS process. The HBT features an f/sub T/ of 50 GHz and f/sub max/ of 80 GHz at V/sub BC/=2 V. The npn transistors are integrated in a 0.35 /spl mu/m CMOS process with poly resistors, MIM capacitors and thick metal 4 on chip spiral inductors.

Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology

This work provides for the first time comprehensive and early guidelines for TSV integration in 10nm node bulk FinFET technology. The key contributors to the TSV proximity induced Keep Out Zone (KOZ) for FinFET devices are analyzed. Advanced TCAD sub-band modeling of the stress impact on the carrier transport is verified by uniaxial wafer bending experiments. This work provides an analytic compact model to derive first KOZ guidelines for scaled FinFET technologies, introducing the KOZ figure of merit K that directly links to KOZ length and area.

High Q inductors and capacitors on Si substrate

In this paper, the impact of conventional silicon technology parameters on the characteristics of passives is studied. For both inductors and capacitors, cost-effective modules, which integrate easily into wiring BEOL (back-end of line) in a conventional silicon technology and provide high Q factor components are presented. For an inductor of 3 nH, designed for 2 GHz frequency applications, and fabricated in thick Cu as an add-on module, Q factor of /spl sim/24 is reached. The metal insulator metal (MIM) capacitor module with outstanding RF performances and a Q factor ranging from 100-1000 in the few GHz frequency range is developed in the Al BEOL. Compact lumped element SPICE models for both components are proposed and verified.

A 400GHz f MAX fully self-aligned SiGe:C HBT architecture

An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An fMAX value of 400GHz is reached by structural as well as intrinsic advancements made to the HBT device.

Lateral and vertical scaling of a QSA HBT for a 0.13/spl mu/m 200GHz SiGe:C BiCMOS technology

A 200 GHz F/sub t/ SiGe:C HBT has been integrated into a 0.13 /spl mu/m BiCMOS technology. A previous generation low complexity quasi self-aligned architecture (QSA) is scaled down both in a lateral and vertical way. Lateral sizing is obtained by using present-day step and scan tools. Vertical sizing is achieved by reducing the thermal budget of the active module and by an aggressive scaling of the SiGe:C base epitaxial layer. A deep trench module, featuring a thick oxide liner, has been developed. Excellent DC parameters and peak Ft/Fmax values of 200/160 GHz are demonstrated. The CMOS device characteristics remain unchanged by applying low thermal budget processing in the bipolar module.

On the Use of a SiGe Spike in the Emitter to Improve the

Aggressive vertical scaling of SiGe HBTs has yielded impressive values for the cut-off frequencies (fT), but these HBTs often suffer from too high current gains. This leads to low values for the open-base breakdown voltage (BVCEO). In this letter we demonstrate the use of a SiGe spike in the emitter as a practical method to increase the base current. Hence, the breakdown voltage is increased. At the same time, the device RF performance is not affected, which leads to a significant improvement in the fTxBVCEO product