Jie Li Aw

Development of bonding process for high density fine pitch micro bump interconnections with wafer level underfill for 3D applications

Realization of 3D IC packaging is mainly depends on the success of fine pitch micro bump bonding process for thin chips stacking and reliability of micro bump interconnections between stacked chips. The uniformity of micro bumps is the critical requirement to achieve good micro bump bonding, and the chip warpage during bonding and underfilling of micro gaps between stacked chips is key challenge in 3D IC packaging. In this work, The FEM modeling and simulations has been carried out to understand the effect of the package parametric on chip warpage and results revealed that chip thickness and substrate thickness has significant effect on chip warpage. The warpage of the test chip with TSVs is lower when compared to test vehicle without TSVs. The fabrication process has been optimized to achieve uniform high density fine pitch micro bumps of 10 μm diameter at 20 μm pitch. Flip chip bonding processes for 20 μm pitch micro bumps with and without pre-applied wafer level underfill material are optimized using conventional reflow and thermal compression bonding (TCB) respectively. Capillary underfill process is also optimized for micro gaps of less than 20 μm and achieved void free underfilling. Thermal compression bonding temperature and force profiles are optimized for micro bumps with pre-applied wafer level underfill material, and achieved good micro bump joints with void free underfilling. Cross-sectional analysis revealed good micro bump joints with and without pre-applied underfill materials and CSAM analysis revealed void free underfilling is feasible using capillary underfilling as well as TCB with pre-applied wafer level underfill. Finally, this paper demonstrated bonding process for high density fine pitch micro bumps for thin large chips stacking which required for 3D IC packaging application.

Chip to wafer bonding for three-dimensional integration of copper low K Chip by stacking process

Industry is adopting three-dimensional integration of Cu-low k Chip with micro-solder bumps by stacking process to increase the functionality and performance of the device. Cu/low k is known to be very fragile and required special packaging process to prevent early delamination issues. Stacking of thin chips with micro-solder bumps need to be carried out without causing solder squeezing, solder non-wetting and also die crack due to improper bonding parameters. In this study, six Cu/low k chips were bonded to another Cu/low k wafer using wafer level pre-applied underfill. The chip used is of size 12mm × 12mm × 0.07mm and consists of peripheral micro-solder bumps at 80μm pitch with SnAg solder cap. The chips were pre-coated with wafer level underfill. Bonding process parameters were evaluated and the optimum parameters determined for the six die stack assembly. Entrapment of underfill material inside the solder material was observed in the bonded samples and this issue was overcome by removing the underfill material above the solder bump through surface planarisation. The developed die stacking successfully demonstrated on C2W application.

Process development of 10μm pitch Cu-Cu low temperature bonding for 3D IC stacking

A low temperature <;200°C Cu-Cu bonding process is developed for 3D IC stacking application. To prepare and activate good copper surface, three planarization processes and two surface treatment methods are studied in details and compared. Best surface treatment method is identified. It is found that good Cu-Cu direct bonding with high shear strength is achieved by the developed process and verified by the cross sectional structure. Low temperature Cu-Cu bonding for 3D IC applications is demonstrated by a high density Cu bump array structure with 10 μm pitch and 5 μm diameter. Chip-to-chip bonding approach is used for 3D IC stack bonding. Final cross sectional and daisy chain electrical measurement showed good connectivity of micro bump joints.

Fine pitch solder-less bonding using ultrasonic technique

Industry is adapting micro-bumps in the device structures in order to having module with multiple functions and capabilities within smaller area. Micro-bumps is coated with Tin (Sn) cap to facilitates solder interconnects formation between the chip and substrate. Electrochemical migration failure is a known issue related to flux residue on the solder joints after the thermal compression of the chip with solder cap micro-bumps on substrate. Electromigration is another issue related to shrinking interconnects. It is related to atomic displacement in a conductor line due to an applied current. In this study, the micro bumps are directly bonded to the substrate without solder cap and thus there is no electro migration failure concern. The chip used in this study is of size 7mm × 7mm × 0.05mm and consists of peripheral micro-solder bumps at 40μm pitch with no solder cap. Ultra-sonic process was adopted to form the direct metal to metal joint between the chip and substrate. Ultrasonic process offered several advantages such as lower bonding temperature and shorter bonding duration over thermal compression process. However, the US process demand bumps with good co-planity of less than 0.6μm and good surface finishing. The copper bumps were coated either with TiAu, ENEPIG, and ENEP to prevent oxidation occurring during the bonding process. Detail DOE experiment was conducted to evaluate the bonding quality. Shear test and x-section analysis revealed that chips coated with either TiAu or ENEPIG could form a bond on silicon substrate coated with TiAu with optimized US parameters. The developed US bonding process successfully demonstrated on C2C application.

Direct eutectic AuSn solder bumping on Al bond pad surface using laser solder ball jetting

Au-rich eutectic AuSn (Au80wt%-Sn20wt%) solder ball alloy is extensively used in MEMS and optoelectronics packaging, for providing flip-chip solder bump interconnections. In this paper, we will look into the possibility of using laser solder ball jetting process for direct eutectic AuSn solder bumping on Al bond pad surface, and compare with eutectic AuSn solder bumping on Al bond pad with Ti/Ni/Au UBM structure. The laser jetted eutectic AuSn solder bumps were observed to wet and form hemi-spherical bumps on the Al bond pad surface, with and without UBM structure. FIB-EDX analysis of the laser jetted eutectic AuSn solder bump on Al bond pad with UBM structure showed formation of dense islands of Au5Sn IMC layer from the top Au finishing layer of the UBM structure. On the other hand, only a few clusters of Au5Sn IMC were formed near to the solder joint of the laser jetted eutectic AuSn solder bump on Al bond pad surface. Ball shear test on the laser jetted eutectic AuSn solder bumps exhibited average solder shear strength of 4.52g/mil2 and 14.22g/mil2, on Al bond pad surface and Al bond pad with UBM structure respectively. Laser jetted eutectic AuSn solder bumps on Al bond pad surface displayed pad lift failure mode, as compared to failure at Al bond pad layer for Al bond pad with UBM structure. In conclusion, eutectic AuSn solder balls could be bumped onto Al bond pad surface via laser jetting.

Thermal Compression Bonding of 30um Pitch Cu Pillar Microbump on Organic Substrate with Bare Cu Bondpad

This paper reports on the development of packaging technology for the assembly of 30μm pitch micro Cu pillar bump (15μm diameter) on organic FCCSP substrate having bare Cu bondpad without NiAu or OSP surface protection. The assembly was performed by thermal compression bonding (TCB) with non-conductive paste (NCP). Finite element modeling and simulation were carried out to understand the Cu pillar structure impact on the TC reliability. The Cu pillar microbump reliability was assessed by thermal cycling (TC) and electromigration (EM) tests. It was found that by the combination of limiting substrates thermal exposure, shortening the TCB bonding time, and use snap cure NCP can help minimizing the offset between Cu pillar and substrate bondpad during assembly. The presence of larger solder volume reduces the filler particle entrapment severity, crack initiation and propagation thus prolonging the fatigue life of interconnect joints. Given sufficient solder cap volume (16mm height), the 15μm diameter, 30μm pitch Cu pillar interconnect has passed MSL3+3x260°C reflow, high temperature storage at 150°C for 1000hours and 1,000x thermal cycle test at -55°C/+125°C extreme temperatures.

Intuitive and inexpensive method to evaluate flip chip bonding parameters of micro bump with wafer-level underfill material using glass substrate

Flip chip bonding of chips coated with wafer-level underfill over optically transparent glass substrate allows ease of inspection of flip chip bonding quality immediately, without the use of equipment such as SEM, CSAM or the need for highly-trained staff to interpret results. This method is inexpensive to implement, while intuitive to the engineer identifying responses to parametric changes in the flip chip bonding process. Our work complements the existing tomography techniques used to evaluate flip chip quality and reduces the amount of laborious cross-sectioning needed, adding new perspectives to evaluating flip chip bonding quality. We identified indicators of good bonding responses to our process parameters in bonding wafer-level underfill chips over glass substrate. This allows relationships to be quickly established and phenomena to be assigned. This evaluative method was inexpensive to implement, and with results that are intuitive to interpret.

Low temperature bonding studies of Au-studs and AuSn-solder bumps on Au-surface using ultrasonic energy

Conventional flip chip bonding requires heating process to enable solder to melt and electrically conductive adhesives to cure. Applying ultrasonic dose, successful flip chip bonding can be achieved at lower temperatures and bonding pressures. Using ultrasonic flip chip bonding is attractive as the reduction in bonding temperature reduces processing time, by reducing time taken for ramping up and cooling down of bonding arm in thermal compression; it also reduces the mismatch of coefficient of thermal expansion (CTE) between the chip and substrate during bonding compared to thermal compression bond and flux and reflow process. In this study, feasibility of room-temperature ultrasonic flip chip bonding of eutectic AuSn solder and Au-stud bumps was evaluated. Design of experiment was carried out on Argon and Hydrogen plasma process as a pre-flip chip cleaning treatment. Investigation of critical ultrasonic flip chip bonding parameters such as ultrasonic power, bonding force and chuck temperature was carried out. In the full manuscript, details of the experimental trials and results of room-temperature bonding of Au-studs and eutectic AuSn solder bumps on Au-surface would be discussed.

Thermal compression bonding with non-conductive adhesive of 30μm pitch Cu pillar micro bumps on organic substrate with bare Cu bondpads

The assembly capability of 30μm ultra-fine pitch Cu pillar flip chip interconnect on a two-layer FCCSP organic substrate with a chip size of 8mm × 8mm × 0.1mm chip was demonstrated by using thermal compression bonding with non-conductive paste (TCB-NCP) to mitigate the issue of coefficient of thermal expansion (CTE) mismatch between silicon chip and organic substrate. A method, developed to quantify post-bonding misalignment, was used to study the effects of different bonding approaches. This paper reports on details of the bill of materials (BoM); description of method to determine mis-alignment; the effects of different bonding approach; assembly challenges; and reliability assessment involving the solder cap volume effects on flip chip joint fatigue life under temperature cycling tests.

Process development and optimization for high temperature endurable flip chip interconnection in SiC high power module

Integrated Circuited devices fabricated on SiC instead of Si allows higher operating temperatures for the future automotive, aerospace, and green and renewable energy industry. With higher temperature interfaces and contacts between the chip and package, new packaging interconnection materials able to sustain high temperature operations need to be explored. This work demonstrates the assembly of a dual-side cooled high power 3-phase inverter module that was 32mm × 30mm with 6 SiC DMOSFET attached by flip chip technology. Rheological modeling using FVM (Finite Volume Method) based simulation was carried out and validated for the dispense pattern of silver sintering material used in high power electronics flip chip attach. Further details of assembly process flow, assembly challenges, reliability assessment and future works will be discussed in the full manuscript.