Mian Zhi Ding

Study on Process Induced Wafer Level Warpage of Fan-Out Wafer Level Packaging

Fan-out wafer level packaging (FO-WLP) technology has lots of advantages of small form factor, higher I/O density, cost effective and high performance. However, wafer warpage is one big challenge during wafer process, which needs to be addressed for successful process integration. In this study, methodology to understand and reduce wafer warpage at different processes is presented in terms of geometry design, material selection, and process optimization through finite element analysis (FEA), theoretical calculation and experimental data. Quick wafer warpage evaluation method is proposed and compared with FEA results for the molded wafer. Wafer process dependent modeling is established and results are validated by experimental data for both mold-first and RDL-first methods. Key parameters are identified based on FEA modeling results: thickness ratio of die to total mold thickness, compression molding condition, molding compound and support wafer materials, dielectric material and Cu RDL design.

Study on silver sintered die attach material with different metal surfaces for high temperature and high pressure (300°c/30kpsi) applications

In this study, Silver sintering material is being evaluated on different metal surfaces for high temperature storage and high temperature plus high pressure test up to 300°C/30kpsi. Three different type of Alumina based ceramic substrates (gold, silver and copper metal finishes) are used as test vehicle in this evaluation. Die attach material and process quality has been evaluated in terms of die shear strength before and after high temperature storage for gold and silver surfaces, further study is the evaluation for the combined test with high temperature and high pressure (HTHP) for plasma treated metal surfaces (silver, gold and copper) and failure mode analysis. Silver-filled epoxy and high temperature epoxy materials are also used as references to make comparison with sintered materials at high temperature storage. After high temperature (300°C) storage test for 500 hours, shear strength of silver surface samples is increased from average shear strength of 17.96N/mm2 to 25.97N/mm2. However, shear strength of gold surface finished (ENEPIG) samples are decreased drastically from average shear strength of 14.78N/mm2 to 0.30N/mm2. A porous layer is observed at the interfaces near the dense Au/Ag alloy between Ni/Pd/Au finished surface and Ag sintering layer where the interfacial failure mode is happened. High temperature (300°C) and high pressure (30kpsi) storage test samples for 500 hours shows relatively higher shear strength for both silver surface and ENEPIG surface while degradation happened on the bare copper surface. After combined HPHT test (300°C/30kpsi/500hours), gold layer in ENEPIG surface is diffused into palladium and nickel layers without creating a porous layer near the Au/Ag alloy and the exhibits good shear strength results which is significantly different behavior from the high temperature storage without pressure. SEM and EDX are used to analyze the cross-sectioned layers after HPHT aging tests. Silver sintering on copper surface shows the lowest shear strength among Ag, Au and Cu substrates. Au substrates has an average shear strength of >20N/mm2, which is higher than Ag substrate which has an average shear strength of >10.9N/mm2.

Evaluation of laser solder ball jetting for solder ball attachment process

Due to the perpetual push in microelectronic industry for miniaturization and better performance, the density of input/output counts on the electronic packages is multiplying within a given area. Conventional flux-based solder ball attachment process is fast reaching its bottleneck in satisfying the more restrictive pitch tolerances, and assembling challenges in optoelectronics and micro-electromechanical systems (MEMS) packages. To meet the new packaging requirements, a new flux-less laser solder ball jetting technology has been developed. Despite the various advantages which laser solder ball jetting can offer, it has not been extensively reported. In this paper, fine pitch laser solder ball jetting at 200μm pitch was demonstrated using 120μm SAC305 solder spheres. The reliability of the laser jetted bumps was evaluated and compared against the flux-based reflowed bumps, by subjecting the bumps under high temperature storage (1250C for 24hrs, 500hrs and 1000 hrs) and multiple reflow (5 and 10 times). The quality and reliability of the solder joints were quantified through the solder ball shear test, cross-sectioning, energy dispersive x-ray (EDX) spectroscopy analysis and scanning electron microscopy (SEM) imaging. From our results, laser jetted bumps showed high initial average shear strength of 10.70g/mil2, which eventually decreased to 6.96g/mil2 after 24 hours. Comparing the laser jetted bumps against the flux-based reflowed bumps after 1000 hours of thermal aging and 10 times of reflow, the average shear strength values were persistently higher and the measurements of the IMC thickness were constantly lower. Hence, laser solder ball jetting has proven to be an attractive and alternative solder ball attachment method for strong and reliable solder interconnections.

Thermo-compression bonding for 2.5D fine pitch copper pillar bump interconnections on TSV interposer

The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption requirements. To meet these challenges, electronic package design uses thinner chips with fine pitch bumping. There is active development in 2.5D and 3D IC packages with through silicon via (TSV). Tighter interconnection in addition to the increased density in the circuit in 2.5D and 3D IC systems provide higher performance with lower power consumption [1]. In addition, there is increased in the demand for fine pitch copper pillar bumping due to the lower silicon node, chip size reduction and TSV technology. Fine pitch interconnections are required in 2.5D and 3DIC integration for the demands of electrical continuity and high performance. In the existing interconnection methods, solder micro bumps have received a great deal of attentions because of its low material and process cost [2]. The major difference of copper pillar FC bonding process comparing to traditional FC bonding process is the reduction of the solder volume on each solder bump. As a result, there is no advantage of self-alignment of the solder during solder reflow process. Flip-chip bonder having accurate chip placement capability is needed to ensure good solder joint formation. Conventional reflow method is still applicable for sizable solder bump of diameter being greater than 100 μm and larger than 150μm pitch [3]. The post underfill processes such as capillary underfill (CUF) and molded underfill (MUF) can be followed after the solder joints are formed. On the other hand, when the pitch of bumps and/or the thickness of the FC go down further, FC with copper pillar bumps bonded by TC process would be one of the solutions for fine-pitch FC applications. It has been shown that the bump pitch can be reduced to as small as 50 μm (inline pitch). This process also allows for better control on the solder squeezed out effect. However this process requires tight control on (i) the planarization between the FC and the bonding substrate and (ii) the stand-off of each solder joint. Good process parameters have to be established to ensure no solder collapse or open joint.

2.5D through silicon interposer package fabrication by chip-on-wafer (CoW) approach

In this paper, the fabrication process and results of 2.5D through silicon interposer (TSI) package using polymer based RDL and chip-on-wafer (CoW) stacking-first approach is presented. The through silicon interposer is fabricated on a 300 mm silicon substrate with Cu filled vias of aspect ratio of 1:10. Fine-pitch Cu RDL using semi-additive process and polymer based dielectric is used to form the 3 layer of rerouting layer on front-side. Chips with micro-bumps are flip chip assembled onto the under bump metallization (UBM) of the 12 inch interposer substrate using thermal compression bonding via chip-on-wafer (CoW) format on the thick interposer substrate A wafer level molding process is used to form the over-mold encapulation over the assembled chips. The over-mold encapsulation is mechanically thinned down to reduce the warpage of the molded interposer and temporary bonded to a silicon carrier. Mechanical-grinding and chemical mechanical polishing (CMP) is used to expose the Cu vias from the backside. Cu-RDL process is used to form the backside re-routing layer and UBM for solder bumps. The completed interposer wafer is then diced into singulated packages for assembled to printed circuit board (PCB).

Process integration of solder bumps and Cu pillar microbumps on 2.5D fine pitch TSV interposer

The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption requirements. To meet these challenges, electronic package design uses thinner chips with fine pitch bumping. There has been active development in 2.5D and 3D IC packages with through silicon via (TSV). Tighter interconnection in addition to the increased density in the circuit in 2.5D and 3D IC systems provide higher performance with lower power consumption [1]. In addition, the down scaling trend of CMOS technology beyond 28nm node requires smaller chip size for a given input/output (I/O) count, pushing the interconnect pitch smaller and smaller. When the bump pitch is less than 50μm and the gap between the die and substrate is lesser than 25μm, traditional capillary underfill (CUF) material is likely to require a vacuum or pressure assisted process to pull the underfill and fill the gaps without any voids [2]. The narrower gap also makes flux cleaning after reflow more challenging. The development of wafer-level underfills can bring the financial benefits of wafer-level processing to flip chip assembly and packaging. The flip chip assembly is the application of underfill at the wafer level, eliminating the dispense, flow, and separate cure steps associated with assemblies utilizing capillary-flow underfills. In addition, the wafer-level material should include fluxing capabilities similar to no-flow underfills [3]. In this paper we describe the assembly process and challenges of the 100μm thin 2.5D TSV Si interposer to the test substrate and the assembly of three different test chips onto TSV Si interposer using capillary underfill and WL-UF (NST series from Nissan Chemical Industries, Ltd). The TSV Si interposer provides high density multilevel routing on the frontside of the wafers and through-silicon vias (TSVs) to connect the frontside metallization with the backside metallization for connection to the PCB [4].

Development of fluxless flip chip reflow process for high density flip chip interconnect

In flip chip technology, flux is widely used to clean the surface of the solder bumps and the surfaces to be soldered for good wetting of the solder bumps on the conductive bond pads [1]. Moreover, flux helps to keep the flipped chip in position and hold it during die placement and the subsequent reflow process. However, this flux-containing reflow can cause problems and inconveniences. For example, volatile materials are generated when organic fluxes decompose during heating. These volatiles could be trapped in the molten solder and form voids, which degrade mechanical and electrical properties of the solder joints, and affect the subsequent chip bonding process [2]. In addition, flux residues adversely affect underfill interfacial adhesion in the flip chip assembly process. Flux residues must therefore be removed, which is typically done through post-reflow cleaning. With no-clean fluxes, which include a small amount of activators to minimize residues, there is a tradeoff between reduced residues and diminished flux performance. Because of the problems associated with organic fluxes, there is a need to study the fluxless solder reflow process [3]. In this paper, we study the fluxless flip chip reflow process and evaluated the reliability performance for 2 different test dies onto the 100um thin 2.5D TSV Si interposer using a temporary adhesive material. The assembled sample is then subjected to a lead-free reflow profile in vacuum oven with forming acid. One advantage of the temporary adhesive material is that it will evaporate at reflow temperature. Results showed that both test dies passed moisture sensitivity level test level 3 under Jedec standard J-STD-020 (30°C/60%RH) for 192 hours without any underfill delamination.

Integrated electronic and microfluidic packaging for CMOS biosensor chip

In recent years, advanced incorporation of complementary metal oxide semiconductor (CMOS) biosensor chips with sensory microarrays has gained tremendous attention. In this paper, we investigated a maskless approach to microfluidic channel fabrication that integrates seamlessly with CMOS biosensor chip packaging. The microfluidic channels were formed via precisely controlled dispensing of adhesive to define microfluidic dam structures. This was followed by encapsulation of the microfluidic dam with a lid, thereby producing an impervious seal. Four types of commercial adhesives used in medical/implantable devices were evaluated in this study; a silicone-based adhesive, an ultraviolet curable epoxy, an ultraviolet curing acrylate adhesive, and a thermal curing epoxy. The adhesives were evaluated based on the performance criteria such as: (i) critical dimension (CD) of microfluidic channels, (ii) minimum microfluidic dam height, (iii) biocompatibility, and (iv) bond strength of the adhesive between CMOS substrate film to the lid material. The test vehicles comprising of ITO glass lid material, SiN substrate material and various evaluated adhesives, were subjected to burst pressure leak test. From the results obtained, Dow Corning® 3140 silicone-based adhesive has the best performance as a suitable adhesive for microfluidic dam structure formation. Lastly, a seamless approach to integrating electronic and microfluidic packaging through the use of controlled adhesive dispensing and a pick and place assembly tool was demonstrated with the use of Dow Corning® 3140 adhesive for microfluidic biological applications.

Direct eutectic AuSn solder bumping on Al bond pad surface using laser solder ball jetting

Au-rich eutectic AuSn (Au80wt%-Sn20wt%) solder ball alloy is extensively used in MEMS and optoelectronics packaging, for providing flip-chip solder bump interconnections. In this paper, we will look into the possibility of using laser solder ball jetting process for direct eutectic AuSn solder bumping on Al bond pad surface, and compare with eutectic AuSn solder bumping on Al bond pad with Ti/Ni/Au UBM structure. The laser jetted eutectic AuSn solder bumps were observed to wet and form hemi-spherical bumps on the Al bond pad surface, with and without UBM structure. FIB-EDX analysis of the laser jetted eutectic AuSn solder bump on Al bond pad with UBM structure showed formation of dense islands of Au5Sn IMC layer from the top Au finishing layer of the UBM structure. On the other hand, only a few clusters of Au5Sn IMC were formed near to the solder joint of the laser jetted eutectic AuSn solder bump on Al bond pad surface. Ball shear test on the laser jetted eutectic AuSn solder bumps exhibited average solder shear strength of 4.52g/mil2 and 14.22g/mil2, on Al bond pad surface and Al bond pad with UBM structure respectively. Laser jetted eutectic AuSn solder bumps on Al bond pad surface displayed pad lift failure mode, as compared to failure at Al bond pad layer for Al bond pad with UBM structure. In conclusion, eutectic AuSn solder balls could be bumped onto Al bond pad surface via laser jetting.

Development of Chip-to-Wafer (C2W) bonding process for high density I/Os Fan-Out Wafer Level Package (FOWLP)

In the current mobile electronics market, there is a great demand of electronics products with better performance, smaller foot print and greater package functionality with a lower manufacturing cost. Smart phones and tablets are some of the portable electronics devices that require more functions, smaller form factor and reduced power consumption requirements [1]. To address these requirements, the Multi-Chip Fan-Out Wafer Level Package (FOWLP) technology promises an alternative technology for high performance and multi-die packaging in FOWLP technology [2]. In conventional flip chip assembly, the advantages of using Cu pillar and solder micro bumps are mainly because of it allows for fine pitch applications and superior power management in terms of thermal and electrical [3]. The major difference in using copper pillar with solder micro bumps is that the solder volume are significantly reduced on each solder bump. Furthermore, the lesser solder volume on the Cu pillar bumps makes it difficult for solder self-alignment during solder reflow process [4]. Hence it is critical that good chip placement accuracy is needed in the flip-chip bonder for good solder interconnect formation especially for our work in the new RDL-first FOWLP technology with multiple die and high pin count applications [5]. In this paper, we present the chip to wafer assembly for multiple die on the RDL-First FOWLP approach. Chip-to-Wafer assembly is a promising technology for high density package application to overcome the limitation of Wafer-to-Wafer boding in terms of die stacking process yield and bonding placement accuracy on wafers. Our test vehicle is a large multi-chip package of 20×20mm2 fabricated using the RDL-First FOWLP approach. There are 2400 I/Os on the FOWLP package. The C2W flip chip process is done to attach the 3 test chips onto the 3 layers RDL film onto the 12 inch glass carrier with sacrificial layer using the mass reflow method. The assembly process was optimized and samples are built to subject to JEDEC Moisture Sensitivity Test Level 3 for reliability assessment.