F. X. Che

Study on Cu Protrusion of Through-Silicon Via

The through-silicon via (TSV) approach is essential for 3-D integrated circuit (3-DIC) packaging technology. TSV fabrication process, however, is still facing several challenges. One of the widely known challenges is via protrusion. Annealing a TSV wafer puts the copper (Cu) TSVs under high stress and may form a protrusion where the Cu is forced out of the blind TSV. This phenomenon occurs because the large mismatch in the coefficient of thermal expansion between Cu via and silicon (Si) surrounding it. Cu protrusion can lead to crack or delamination of the back-end-of-line, thus, it is a risky threat to the metal layer interconnect. Experiments are conducted to characterize the protrusion using several techniques. Scanning electron microscopes and atomic force microscopes are used to observe the protrusion shape and measure the height. An electron backscatter diffraction technique is implemented to study the grain size distribution and evolution inside Cu vias. For the experiment, arrays of 5-

Wafer level warpage modeling methodology and characterization of TSV wafers

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Characterization and management of wafer stress for various pattern densities in 3D integration technology

TSVs are fabricated and annealed in nitrogen gas environment in different temperatures. In this paper, finite element analysis (FEA) is carried out to study the Cu protrusion under different annealing conditions. Correlation between numerical results and experimental data is then carried out. Based on the verified FEA methodology, several parametric studies are then conducted, including the effect of via diameter, depth, pitch, annealing temperature, and duration on Cu protrusion and TSV stress. The simulation results help to understand and solve the key problem in TSV fabrication process and reliability challenge.

Structure Design Optimization and Reliability Analysis on a Pyramidal-Shape Three-Die-Stacked Package With Through-Silicon Via

Through-silicon-via (TSV) approach has been widely investigated recently for three-dimensional (3D) electronic packaging integration. TSV wafer warpage is one of the most challenges for successfully subsequent processes. In this work, wafer level warpage modeling methodology has been developed by finite element analysis (FEA) method using equivalent material model. The developed modeling methodology has been verified by numerical results and experiment data. With using the developed model, wafer warpage has been simulated and analyzed by considering different factors such as annealing temperature, Cu overburden thickness, TSV depth and diameter. Simulation results show that wafer warpage increases with increasing annealing temperature and increasing Cu overburden thickness. Such findings have been successfully used in the TSV process optimization to reduce wafer warpage after annealing process. Submodeling methodology has also been developed to determine wafer stress accurately. Wafer bending stress is larger at wafer surface and close to the TSV edge. Bending stress is higher at the edge of TSV with finer pitch.

Study on Process Induced Wafer Level Warpage of Fan-Out Wafer Level Packaging

In the current 3D integration technology, the control of wafer warp is needed to ensure uniform photolithography, good bonding areas and other major processes that requires flat wafer surface. In this paper, we found out that the wafer warpage was increased with increasing TSV density. The highest wafer warpage was observed after Cu annealing base on step by step warpage monitor. Wafer warpage reduction is achieved by process stage modification.

Extremely high temperature and high pressure (x-HTHP) endurable SOI device & sensor packaging for deep sea, oil and gas applications

In this paper, the reliability of a pyramidal-shape three-die-stacked package with through-silicon via (TSV) is studied experimentally and numerically. The initially designed microbumps are located peripherally along the edge of the TSV die, which induces a concentrated bending force on the lower die when the upper die is stacked. Finite-element (FE) simulation results show that such bump layout induces large stress and deflection in the lower die under the die-stacking process. Three-point bend tests were conducted to determine the die strength. Die-stacking experiments were also carried out. The experimental results show that the bottom die cracks when the middle die is stacked and the middle die cracks when the top die is stacked even with a small stacking force. Consistent results have been obtained among FE simulation, die strength bend test, and die-stacking experiments. An optimal bump layout design is proposed, which adds some dummy bumps on the central area of the die to support the bending force induced by the die-stacking process. The optimal design significantly reduces the die stress level and deflection. Finally, a successful die-stacking process is achieved even using a larger stacking force.

Comprehensive study on reliability of chip-package interaction using Cu pillar joint onto low k chip

Fan-out wafer level packaging (FO-WLP) technology has lots of advantages of small form factor, higher I/O density, cost effective and high performance. However, wafer warpage is one big challenge during wafer process, which needs to be addressed for successful process integration. In this study, methodology to understand and reduce wafer warpage at different processes is presented in terms of geometry design, material selection, and process optimization through finite element analysis (FEA), theoretical calculation and experimental data. Quick wafer warpage evaluation method is proposed and compared with FEA results for the molded wafer. Wafer process dependent modeling is established and results are validated by experimental data for both mold-first and RDL-first methods. Key parameters are identified based on FEA modeling results: thickness ratio of die to total mold thickness, compression molding condition, molding compound and support wafer materials, dielectric material and Cu RDL design.

Modeling and characterization of Cu wire bonding process on silicon chip with 45nm node and Cu/low-k structures

The extremely high temperature and high pressure endurable (250°C/30 kspi) SOI based temperature sensor and voltage regulator module was developed for harsh environment application such as deep sea, oil & gas down-hole drilling and aerospace engine electronics. The hermetically sealed metal casing which can withstand external pressure up to 30 kpsi was designed and optimized through mechanical modeling and characterization. In side of this hermetic casing, the physical layout of SOI devices and ruggedized components for temperature sensor and voltage regulator was fabricated on ceramic substrate assembled by high temperature endurable interconnection materials such as Au-Sn, Au-Ge and Ag sintering materials. The developed modules are tested with specified reliability testing criteria and evaluation results shows that the packaging and interconnection showed still functional after high temperature storage (HTS) test of 250°C for 500 h and temperature cycling condition -55°C~250°C for 500 cycles. Also passed 30 kpsi pressure cycling and other deep sea and down hole drilling environment test. Those results demonstrate that current SOI sensor module with hermetically sealed metal casing packages design, material and process are considered to be applicable for extreme-HTHP application meeting huge demands in automotive, aerospace engine electronics, down-hole drilling, geothermal and deep sea applications for future.

Extremely High Temperature and High Pressure (x-HTHP) Endurable SOI Device and Sensor Packaging for Harsh Environment Applications

Cu pillar technology can cater for high I/O, fine pitch and further miniaturization requirements compared to wire bonding and conventional flip chip technologies. However, chip-package interaction (CPI) for low-k chip is a critical challenge for Cu pillar technology under assembly process and temperature loading due to stiffer Cu pillar structure compared to conventional C4 bump. Thermo-compression bonding (TCB) process was developed and used for fine pitch Cu pillar assembly on Cu/low-k chip to reduce the package warpage and low-k stress. In this study, a novel TCB process modeling methodology using a 2D axisymmetry model with global-local technique was established by considering process condition step by step. The simulation results show that TCB process results in much lower package warpage and low-k stress compared to reflow process. Based on the developed TCB modeling method, the comprehensive parametric studies were conducted to optimize TCB process condition and Cu pillar design for CPI reliability improvement, including Cu pillar structure design, package geometry, and packaging materials selection. The final package and assembly solution was successfully achieved based on suggestions and recommendations provided by numerical simulation results.

Thermal Compression Bonding of 30um Pitch Cu Pillar Microbump on Organic Substrate with Bare Cu Bondpad

Due to the rapid increase of Au price in recent years, there is an emerging trend to use Cu to replace Au in wire bonding because Cu wire not only has lower cost but also has superior electrical, mechanical and thermal properties. However, Cu ball is much harder than Au ball so that there are several challenges for applying Cu wire bond such as excessive deformation of the Al bond pad and dielectric layer crack under the bond pads, especially for low-k structures. In this study, the stress sensors were designed in the test chips and used to measure under pad stress in real-time. Dynamic finite element modeling methodology was developed for wire bonding process and validated by stress measurement. Parametric studies were conducted using numerical modeling to find ways to reduce Al deformation and stresses by adjusting parameters.