Daniel Ismael Cereno

Chip to wafer bonding for three-dimensional integration of copper low K Chip by stacking process

Industry is adopting three-dimensional integration of Cu-low k Chip with micro-solder bumps by stacking process to increase the functionality and performance of the device. Cu/low k is known to be very fragile and required special packaging process to prevent early delamination issues. Stacking of thin chips with micro-solder bumps need to be carried out without causing solder squeezing, solder non-wetting and also die crack due to improper bonding parameters. In this study, six Cu/low k chips were bonded to another Cu/low k wafer using wafer level pre-applied underfill. The chip used is of size 12mm × 12mm × 0.07mm and consists of peripheral micro-solder bumps at 80μm pitch with SnAg solder cap. The chips were pre-coated with wafer level underfill. Bonding process parameters were evaluated and the optimum parameters determined for the six die stack assembly. Entrapment of underfill material inside the solder material was observed in the bonded samples and this issue was overcome by removing the underfill material above the solder bump through surface planarisation. The developed die stacking successfully demonstrated on C2W application.

Thermo-compression bonding for 2.5D fine pitch copper pillar bump interconnections on TSV interposer

The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption requirements. To meet these challenges, electronic package design uses thinner chips with fine pitch bumping. There is active development in 2.5D and 3D IC packages with through silicon via (TSV). Tighter interconnection in addition to the increased density in the circuit in 2.5D and 3D IC systems provide higher performance with lower power consumption [1]. In addition, there is increased in the demand for fine pitch copper pillar bumping due to the lower silicon node, chip size reduction and TSV technology. Fine pitch interconnections are required in 2.5D and 3DIC integration for the demands of electrical continuity and high performance. In the existing interconnection methods, solder micro bumps have received a great deal of attentions because of its low material and process cost [2]. The major difference of copper pillar FC bonding process comparing to traditional FC bonding process is the reduction of the solder volume on each solder bump. As a result, there is no advantage of self-alignment of the solder during solder reflow process. Flip-chip bonder having accurate chip placement capability is needed to ensure good solder joint formation. Conventional reflow method is still applicable for sizable solder bump of diameter being greater than 100 μm and larger than 150μm pitch [3]. The post underfill processes such as capillary underfill (CUF) and molded underfill (MUF) can be followed after the solder joints are formed. On the other hand, when the pitch of bumps and/or the thickness of the FC go down further, FC with copper pillar bumps bonded by TC process would be one of the solutions for fine-pitch FC applications. It has been shown that the bump pitch can be reduced to as small as 50 μm (inline pitch). This process also allows for better control on the solder squeezed out effect. However this process requires tight control on (i) the planarization between the FC and the bonding substrate and (ii) the stand-off of each solder joint. Good process parameters have to be established to ensure no solder collapse or open joint.

Fine pitch solder-less bonding using ultrasonic technique

Industry is adapting micro-bumps in the device structures in order to having module with multiple functions and capabilities within smaller area. Micro-bumps is coated with Tin (Sn) cap to facilitates solder interconnects formation between the chip and substrate. Electrochemical migration failure is a known issue related to flux residue on the solder joints after the thermal compression of the chip with solder cap micro-bumps on substrate. Electromigration is another issue related to shrinking interconnects. It is related to atomic displacement in a conductor line due to an applied current. In this study, the micro bumps are directly bonded to the substrate without solder cap and thus there is no electro migration failure concern. The chip used in this study is of size 7mm × 7mm × 0.05mm and consists of peripheral micro-solder bumps at 40μm pitch with no solder cap. Ultra-sonic process was adopted to form the direct metal to metal joint between the chip and substrate. Ultrasonic process offered several advantages such as lower bonding temperature and shorter bonding duration over thermal compression process. However, the US process demand bumps with good co-planity of less than 0.6μm and good surface finishing. The copper bumps were coated either with TiAu, ENEPIG, and ENEP to prevent oxidation occurring during the bonding process. Detail DOE experiment was conducted to evaluate the bonding quality. Shear test and x-section analysis revealed that chips coated with either TiAu or ENEPIG could form a bond on silicon substrate coated with TiAu with optimized US parameters. The developed US bonding process successfully demonstrated on C2C application.

Intuitive and inexpensive method to evaluate flip chip bonding parameters of micro bump with wafer-level underfill material using glass substrate

Flip chip bonding of chips coated with wafer-level underfill over optically transparent glass substrate allows ease of inspection of flip chip bonding quality immediately, without the use of equipment such as SEM, CSAM or the need for highly-trained staff to interpret results. This method is inexpensive to implement, while intuitive to the engineer identifying responses to parametric changes in the flip chip bonding process. Our work complements the existing tomography techniques used to evaluate flip chip quality and reduces the amount of laborious cross-sectioning needed, adding new perspectives to evaluating flip chip bonding quality. We identified indicators of good bonding responses to our process parameters in bonding wafer-level underfill chips over glass substrate. This allows relationships to be quickly established and phenomena to be assigned. This evaluative method was inexpensive to implement, and with results that are intuitive to interpret.

Stealth Dicing Challenges for MEMS Wafer Applications

In our digital world, microelectromechanical system (MEMS) are here to stay and will open the doors for the next exciting wave in the advancement of technology such as the Internet of Things (IoT). The MEMS devices in wafer forms are fabricated in minute details and eventually singulated into individual units to act as sensing or actuation elements in various applications such as accelerometer and gyroscopes for navigation, in wireless mobile and smart car applications. Handling of such MEMS device requires overcoming many challenges in both fabrication and assembly. Singulation of MEMS device with fragile and sensitive structures is one of the many assembly challenges. In fact, most devices are capped to protect its active moving components that maybe damaged when using conventional singulation method that is by mechanical dicing wherein water splashes or pressure is unavoidable. With the introduction of stealth laser dicing, where micro damage is created internally and through several layers of this damages creates a propagation to eventually separate the wafer upon forced expansion through tape, it became possible for a dry process singulation without damaging the fragile components. However, stealth dicing leverages on infrared waves being transparent only and able to penetrate through smooth surface silicon wafers and at certain resistivity or level of doping to create internal damage on the work piece. As such, stealth dicing process may have difficulty to handle saw street with metallization, heavily doped or high resistivity wafer as in the case of SOI wafer and deep trenches that may surface in some MEMS devices. This created limitations for MEMS designs, processes and materials selection that may not be limited to the active region alone but as well as on the dicing saw street. In this paper we will conduct stealth dicing study on various types of wafer configuration and thus making a clearer assembly process for next generation of mobile applications and the fast growing market of IoT.

Study of C2W Bonding Using Cu Pillar with Side-Wall Plated Solder

Cu-Cu is a prefer choice of interconnects as it offered lower electrical resistance, no risk of shorting between the bump and higher reliability as compared to Cu-Solder Bump. However, Cu-Cu interconnect requests stringent condition such as Cu bump surface topography, flatness, uniformity of pillar array heights and clean bonding surface. From throughput point of view, Cu-Cu bonding is challenging as bonding profile involves long heating duration and high temperature. In this paper, we explore the method to improve the bonding throughput and improve interconnect formation. A novel Cu pillar structure is proposed with center core Cu pillar surrounded by side-wall layer solder. Such Cu pillar array is bonded on a bottom wafer with Cu pads through chip-to-wafer (C2W) method. Study shows the solder located at side-wall offers an assist of temporary tacking the chip on the wafer. Then the entire interconnect forms joint through the use of gang bonder. As the side-wall solder seals individual Cu pillar to corresponding bond pad, it helps to prevent non-contact or void interconnection in pillar array. With the tacking and gang bonding process, a higher throughput process can be realized and actively adopted by industry as it offers lower cost of assembly.

Ultra-fine pitch Cu-Cu bonding of 6μm bump pitch for 2.5D application

Ultra-fine pitch (6μm) interconnects are essential for high-end application-products that demands high speed and high bandwidth inter-chip communication. Achieving Cu-Cu bonding with such a fine pitch is challenging since bond time is too long and bond interface gets easily oxidized. Throughput issue associated with long-bonding time is solved by using 2-step bonding procedure where first step is a temporary bonding and second step is a permanent bonding using a gang bonder. Gaseous formic acid is used to remove surface oxide on Cu surface and wafer level pre applied underfill is used as a tacking material in temporary bonding. Bonding is carried out with dies having 500,000 interconnects and the results show excellent bonding and electrical properties.

Through mold interconnects for fan-out wafer level package

Through mold interconnects (TMI) is a key enabler for fan-out wafer level packaging (FOWLP) for 3D integration. Three different types of TMI have been developed for both mold-first and RDL-first fabrication flow. The three types of TMI consist of laser drilled vias, vertical wire-bonds and Cu pillars interconnect. The process flow and fabrication results of each TMI will be presented in this paper.