John Zimmerman

EUV lithography with the Alpha Demo Tools: status and challenges

ASML has built and shipped to The College of Nanoscale Science and Engineering of the University at Albany (CNSE) and IMEC two full field step-and-scan exposure tools for extreme ultraviolet lithography. These tools, known as Alpha Demo Tools (ADT), will be used for process development and to set the foundation for the commercialization of this technology. In this paper we will present results from the set-up and integration of both ADT systems, status of resist and reticles for EUV, and the plans for using these tools at the two research centers. We will also present the first resist images from one of the tools at the customer site, and demonstrate 32nm half-pitch dense lines/spaces printing as well as 32nm dense contact hole printing.

EUV lithography at chipmakers has started: performance validation of ASML's NXE:3100

With the 1st NXE:3100 being operational at a Semiconductor Manufacturer and a 2nd system being shipped at the time of writing this paper, we enter the next phase in the implementation of EUV Lithography. Since 2006 process and early device verification has been done using the two Alpha Demo Tools (ADTs) located at IMEC in Leuven, Belgium and at the CSNE in Albany, New York, USA. Now process integration has started at actual Chipmakers sites. This is a major step for the development and implementation of EUVL. The focus is now on the integration of exposure tools into a manufacturing flow, preparing high volume manufacturing expected to start in 2013. While last years NXE:3100 paper focused on module performance including optics, leveling and stages, this years update will, in detail, assess imaging, overlay and productivity performance. Based on data obtained during the integration phase of the NXE:3100 we will assess the readiness of the system for process integration at 27nm hp and below. Imaging performance with both conventional and off-axis illumination will be evaluated. Although single exposure processes offer some relief, overlay requirements continue to be challenging for exposure tools. We will share the status of the overlay performance of the NXE:3100. Source power is a key element in reaching the productivity of the NXE:3100 - its status will be discussed as well. Looking forward to high volume manufacturing with EUV we will update on the design status of the NXE:3300B being introduced in 2012 with a productivity target of 125wph. Featuring a 0.33NA lens and off-axis illumination at full transmission, a half pitch resolution from 22nm to 16nm can be supported. In order to ensure a solid volume ramp-up the NXE:3300B will be built on as many building blocks from the NXE:3100 as possible making optimum use of the NXE platform concept.

EUVL system: moving towards production

Single exposure lithography is the most cost effective means of achieving critical level exposures, and extreme ultraviolet lithography (EUVL) is the technology that will enable this for 27nm production and below. ASML is actively engaged in the development of a multi generation production EUVL system platform that builds on TWINSCANTM technology and the designs and experience gained from the build, maintenance, and use of the Alpha Demo Tools (ADTs). The ADTs are full field step-and-scan exposure systems for EUVL and are being used at two research centers for EUVL process development by more than 10 of the major semiconductor chip makers, along with all major suppliers of masks and resist. In this paper, we will present our EUVL roadmap, and the manufacturing status of the projection lens for our first production system. Included will also be some test data on the new reticle pods. Experimental results from ADT showing the progress in imaging (28 nm half pitch 1:1 lines/spaces CDU ~10%), single machine overlay down to 3 nm, and resist complete the paper.

Progress on EUV pellicle development

As EUV approaches high volume manufacturing, reticle defectivity becomes an even more relevant topic for further investigation. Current baseline strategy for EUV defectivity management is to design, build and maintain a clean system without pellicle. In order to secure reticle front side particle adders to an acceptable level for high volume manufacturing, EUV pellicle is being actively investigated. Last year ASML reported on our initial EUV pellicle feasibility. In this paper, we will update on our progress since then. We will also provide an update to pellicle requirements published last year. Further, we present experimental results showing the viability and challenges of potential EUV pellicle materials, including, material properties, imaging capability, scalability and manufacturability.

Performance of the full field EUV systems

The ASML extreme ultraviolet lithography (EUV) alpha demo tool is a 0.25NA fully functional lithography tool with a field size of 26×33 mm2, enabling process development for sub-40-nm technology. Two exposure tools are installed at customer facilities, and are equipped with a Sn discharge source. In this paper we present data measured at intermediate focus of the Sn source-collector module. We also present performance data from both exposure tools, show the latest results of resist exposures including excellent 32-nm half pitch dense staggered and aligned contact hole images, and present the highlights of the first demonstration of an electrically functional full field device with one of the layers made using EUVL in ASMLs alpha demo tool.

Mask aspects of EUVL imaging at 27nm node and below

EUVL requires the use of reflective optics including a reflective mask. The mask consists of an absorber layer pattern on top of a reflecting multilayer, tuned for 13.53 nm. The EUVL mask is a complex optical element with many parameters contributing the final wafer image quality. Specifically, the oblique incidence of light, in combination with the small ratio of wavelength to mask topography, causes a number of effects which are unique to EUV, such as an HV CD offset. These so-called shadowing effects can be corrected by means of OPC, but also need to be considered in the mask stack design. In this paper we will present an overview of the mask contributors to imaging performance at the 27 nm node and below, such as CD uniformity, multilayer and absorber stack composition, thickness and reflectivity. We will consider basic OPC and resulting MEEF and contrast. These parameters will be reviewed in the context of real-life scanner parameters both for the NXE:3100 and NXE:3300 system configurations. The predictions will be compared to exposure results on NXE:3100 tools, with NA=0.25 for different masks. Using this comparison we will extrapolate the predictions to NXE:3300, with NA=0.33. Based on the lithographic investigation, expected requirements for EUV mask parameters will be proposed for 22 nm node EUV lithography, to provide guidance for mask manufacturers to support the introduction of EUV High Volume Manufacturing.

Impact of an etched EUV mask black border on imaging: part II

The image border is a pattern free dark area around the die on the photomask serving as transition area between the parts of the mask that is shielded from the exposure light by the Reticle Masking (ReMa) blades and the die. When printing a die at dense spacing on an EUV scanner, the reflection from its image border overlaps with the edges of neighboring dies affecting CD and contrast in this area. This is related to the fact that EUV absorber stack has 1-3% reflectance for actinic light. For a 55nm thick absorber the induced CD drop at the edges is found to be 4-5 nm for 27 nm dense lines. In this work we will show an overview of the absorber reflection impact on CD at the edge of the field across EUV scanner generations, for several imaging nodes and multiple absorber heights. Increasing spacing between dies on the wafer would prevent the unwanted exposure but results in an unacceptable loss of valuable wafer real estate thereby reducing the yield per wafer and is thus not a viable manufacturing solution. In order to mitigate the reflection from the image border one needs to create a so called black border. The most promising approach is removal of the absorber and the underlying multilayer down to the low reflective LTEM substrate by multilayer etching. It was shown in the previous study that the impact on CD was reduced essentially for 27 nm dense lines exposed on ASML NXE:3100. In this work we will continue the study of a multilayer etched black border impact on imaging. In particular, 22 nm lines/spaces imaging on ASML NXE:3300 EUV scanner will be investigated in the areas close to the black border as well as die to die effects. We will look closer into the CD uniformity impact by DUV Out-of-Band light reflected from black border and its mitigation. A possible OPC approach will also be evaluated.

Impact of an etched EUV mask black border on imaging and overlay

There are multiple mask parameters that can be tuned to optimize the lithographic performance of the EUV photo mask[1]. One of them is the absorber height. A reduction of the absorber height allows, for example, a higher resolution patterning on mask and reduces the OPC needed for shadowing correction[1][2][5]. Downside of a thinner absorber is the increased reflectivity which manifests itself not only in the image field (contrast loss) but also in the so called light shield area or image border. The image border is a pattern free (absorber covered) area around the die on the photo mask forming the transition area between the part on the mask that is completely shielded from the exposure light by the Reticle Masking (REMA) blades and the die. The image border accommodates the finite REMA placement accuracy and the half shadow of the REMA blades allowing close spaced die printing on the wafer. When printing a die at dense spacing, which is common practice in a production environment, the image border will overlap part of the neighboring die. This causes actinic EUV and DUV out of band light reflection from the image border exposing the overlapped die area and affecting CD and contrast at the edges of the dies. For a 44 nm thick absorber we found a CD impact of 8 nm for 32 nm dense lines[3] whereas for a 55 nm thick absorber the effect was 4 nm for 27 nm dense lines[7]. Increasing the die spacing would prevent this unwanted exposure but results in an unacceptable loss of valuable wafer real estate thereby reducing the yield per wafer and is thus not a viable manufacturing solution. Optical Proximity Correction (OPC) using ASML Brion’s Tachyon NXE model at the edges of the die was proposed as possible solution to this problem[3]. An alternative is to create a so called Black Border: the reflectivity in the image border is reduced to a sufficiently low level by for example increasing the absorber thickness, add a special coating or replace the absorber with a low reflective material[4][5]. The most radical solution is removal of the absorber and the underlying multilayer down to the low reflective substrate, so-called multilayer etching[4][6]. In this paper we will present the effects of such a Black Border created by a multilayer etch on features and their placement on the reticle and the impact on CD of 27 nm dense lines on the wafer. By comparing the wafer CDU printed with and without Black Border we will determine how well the image border effect is mitigated by the multilayer etching.

EUV High-NA scanner and mask optimization for sub 8 nm resolution

EUV lithography for resolution below 8 nm half pitch requires the numerical aperture (NA) of the projection lens to be significantly larger than the current state-of-the-art 0.33NA. In order to be economically viable, a throughput in the range of 100 wafers per hour is needed. As a result of the increased NA, the incidence angles of the light rays at the mask increase significantly. Consequently the shadowing and the variation of the multi-layer reflectivity deteriorate the aerial image contrast to unacceptably low values at the current 4x magnification. The only solution to reduce the angular range at the mask is to increase the magnification. Simulations show that we have to double the magnification to 8x in order to overcome the shadowing effects. Assuming that the mask infrastructure will not change the mask form factor, this would inevitably lead to a field size that is a quarter of the field size of current 0.33NA step and scan systems. This would reduce the throughput of the high-NA scanner to a value significantly below 100 wafers per hour unless additional measures are taken. This paper presents an anamorphic step and scan system capable to print fields that are half the field size of the current full field. The anamorphic system has the potential to achieve a throughput in excess of 150 wafers per hour by increasing the transmission of the optics as well as increasing the acceleration of the wafer stage and mask stage. This makes it an economically viable lithography solution. The proposed 4x/8x magnification is not the only logical solution. There are potentially other magnifications to increase the scanner performance while at the same time reducing the mask requirements.

Evaluation of an e-beam correction strategy for compensation of EUVL mask non-flatness

In extreme ultraviolet lithography (EUVL), mask non-flatness contributes to overlay errors in EUVL scanners. Tight non-flatness targets are required to meet future overlay; for example, the International Technology Roadmap for Semiconductors (ITRS) requires that substrate non-flatness will need to decrease to 36 nm peak-to-valley in 2013. To meet these tight non-flatness values, suppliers must use aggressive polishing steps, adversely impacting substrate yield and mask blank cost of ownership. An alternative option is to use image placement corrections at the writing step of the reticle to compensate for the predicted impact of the non-flatness pattern placement errors, which would allow the specifications to be relaxed. In this paper, we will present the results of using e-beam image placement corrections during mask writing to compensate for mask non-flatness. A low thermal expansion material (LTEM) substrate with about 500 nm of nonflatness was employed. Three different compensation methods were used to calculate the predicted image placement errors based upon the mask non-flatness, including the expected errors from scanner chucking. The mask was designed to use a repeating set of four ASML alignment marks (XPA marks) across the mask. During e-beam writin, one mark was left uncompensated, and the three different compensation methods were applied to the remaining marks. The masks were exposed using the ASML alpha demo tool (ADT). An overview of the viability of e-beam correction methodologies to compensate for mask non-flatness is presented based upon the wafer overlay results.