Joke De Messemaeker

Impact of post-plating anneal and through-silicon via dimensions on Cu pumping

Irreversible extrusion of Cu from through-silicon vias (TSVs) during high-temperature processing steps presents an important potential back-end-of-line (BEOL) reliability issue. Commonly this reliability risk is mitigated by introducing an anneal after Cu plating for TSV fill. This paper presents the impact of the post-plating anneal temperature and time on residual Cu pumping during a sinter for 20 min at 420 °C, for two different TSV dimensions. Using optical profilometry, in total ~ 4000 TSVs were measured, allowing detailed statistical analysis. Within one sample the Cu pumping values were found to be log normally distributed, implying an intrinsically large spread. Lower residual Cu pumping values were found in TSVs annealed at higher temperatures and for longer times, with the sinter conditions of 20 min at 420 °C confirmed as optimal post-plating anneal conditions. The larger TSVs showed more pumping in the average TSV, but at the tail of the distribution the Cu pumping behavior was the same as for the smaller TSVs. This implies that the impact of Cu pumping on BEOL reliability is identical for both sets of TSV dimensions, suggesting that the impact of Cu pumping on BEOL reliability is not necessarily reduced by reducing TSV dimensions.

Correlation between Cu microstructure and TSV Cu pumping

Cu pumping is the irreversible extrusion of Cu from Cu-filled through-silicon vias (TSVs) exposed to high temperatures during back-end of line (BEOL) processing. The distribution of Cu pumping values over the TSVs of a single wafer has a large intrinsic spread. As potential BEOL reliability issues due to Cu pumping will first occur at the highest pumping TSVs, they can be mitigated if the fundamental cause for this large intrinsic spread is known and under control. This paper describes a clear correlation between Cu pumping and TSV Cu microstructure based on the grain size at the top of 5×50 μm TSV, disregarding twin boundaries. For the mitigation of TSV Cu pumping the ideal microstructure was shown to consist of a single grain spanning the whole TSV cross section, bringing down the highest measured Cu pumping value from 248 nm to 73 nm. This effect was attributed to the absence of rapid diffusion paths and grain boundary sliding ability.

On the impossibility of multi-pass equal-channel angular drawing

Abstract Experimental results and numerical calculations show that multi-pass equal-channel angular drawing (ECAD) will be of little technical use because of the important cross-sectional reduction accompanying the shear deformation imparted by the process. Continuous equal-channel deformation without section reduction can only be performed by techniques based on rolling impulsion or hydrostatic ECA pressing.

Effect of test structure on electromigration characteristics in three-dimensional through silicon via stacked devices

Electromigration failure locations in three-dimensional (3D) interconnect structures with high-aspect-ratio through silicon vias, (TSVs, Φ5 × 50 µm2) connected to 40-µm-pitch CuSn solder joints have been identified using test structures which were designed to avoid failures in the back-end-of-line (BEOL). The resistance of the structures with the TSV and bump connections showed a continuous increase until failure. For the structures without a bump connection, where only TSV and re-distributed line (RDL) were the electrically connected, the resistance remained constant prior to the final failure. From cross-sectional analyses after the test, the failure locations were identified at the TSV bottom or at the bump bottom. The location of void formation was changed by applied current direction. The flux divergence generated by the barrier metal and the reservoir effect plays a crucial role in the void formation, and each failure mode is considered to have a different impact on the reliability performance.

Reliability concerns in copper TSV's: Methods and results

Due to their large volume and close proximity to devices, the reliability of copper TSVs is a concern, both with respect to mechanical stresses induced by the TSV in the Si and with respect to copper drift into the liner and the Si. This abstract summarizes recent achievements obtained in imecs 3D-reliability work package where above mentioned reliability concerns are evaluated in detail. To study the impact of mechanical stresses induced by the TSV in the Si, the saturation drain currents Id of transistors have been used as stress sensors. The offset of the Id of transistors closer to a TSV with respect to transistors far away from a TSV has been studied, both directly after processing and after thermal storage and thermal shock. It is shown that stresses generated by the TSV in the Si increase after thermal storage above certain temperatures while thermal shock reduces these stresses. The first is attributed to stress relaxation at high temperatures, while the latter is attributed to cracking/delamination at critical interfaces. To study continuity in TSV-barriers, a method, further referred to as dual ramp rate IVctrl, is introduced. The method consists of controlled current-voltage sweeps at different rates. The difference in breakdown fields for different ramp rates allows estimating TDDB (=Time Dependent Dielectric Breakdown) field acceleration parameters. Applying a negative voltage to the TSV (-V) does not allow copper to drift into the liner, while when applying a positive voltage (+V) to the TSV, copper can drift into the liner in case of a defective, non-continuous barrier. Comparing TDDB field acceleration parameters of -V versus +V tests gives insight in barrier properties. In our study, weak reliability is observed in systems where the TSV-barriers are not continuous.

Structural Evolution of IF Steel during Annealing after ECAP

IF steel processed by equal channel angular pressing to an equivalent strain of 9.2 via route BA was annealed for different times at 500°C and 600°C. At both temperatures the microstructural evolution shows continuous recrystallization followed by grain growth, in absence of primary recrystallization. At 600°C a slightly bimodal grain size distribution develops.

Reliability Challenges Related to TSV Integration and 3-D Stacking

This article identifies four major reliability challenges related to TSV-based 3-D integrated circuits and their solutions that are being developed at imec.

Impact of Cu TSVs on BEOL metal and dielectric reliability

Cu pumping of through silicon vias (TSV) may result in deformations of the Cu/low-k interconnect wiring above the TSVs and affect the back-end-of-line (BEOL) metal and dielectric reliability. We investigate the impact of Cu TSVs on the BEOL reliability, including stress induced voiding (SIV) of Cu vias on top of the TSV and the dielectric reliability of both inter- and intralevel low-k materials in Cu damascene interconnects. Possible solutions to mitigate the reliability risks are also discussed.

Microstructure simulation of grain growth in Cu through silicon vias using phase-field modeling

In this paper, a time-efficient 3D phase-field model, for simulating grain growth in Through Silicon Via (TSV) is presented. This model is modified to model grain growth in the cylindrical shape of a TSV to capture the effect of temperature in its microstructure. The data generated from this simulation is used to explain large distribution of Cu pumping (i.e. non reversible thermal expansion of TSV). To achieve this, generated results must be used as an input in a Finite Element Model of a TSV structure to study the effect of grain growth and asymmetry in distribution of Cu pumping. Results generated from a sample FEM model with grain structure input confirms this capability.

Thermal compression bonding of 20 μm pitch micro bumps with pre-applied underfill — Process and reliability

Thermal compression bonding (TCB) process in combination with a pre-applied underfill material has been developed and investigated for assembling 20 μm pitch Sn-based micro bumps. It is found bonding force has a profound impact on the joint formation behavior. A low bonding force produces bump joints with heavier underfill entrapment and incompletely reacted solder. A higher bonding force leads to more solder squeezing-out, leaving a thin and completely reacted inter-metallic compound (IMC) layer in the joints. Electrical measurement of the daisy chains on the as-bonded chips does not reveal any significant difference between the samples made with different bonding forces. The reliability of the two types of joints were further studied in two post-bonding tests, namely the resistance measurement of daisy chains at an elevated temperature and stack-level thermo-cycling test. Both tests show a better reliability performance from the bump joints with less underfill entrapment and completely reacted IMC layer.