Olalla Varela Pedreira

Impact of post-plating anneal and through-silicon via dimensions on Cu pumping

Irreversible extrusion of Cu from through-silicon vias (TSVs) during high-temperature processing steps presents an important potential back-end-of-line (BEOL) reliability issue. Commonly this reliability risk is mitigated by introducing an anneal after Cu plating for TSV fill. This paper presents the impact of the post-plating anneal temperature and time on residual Cu pumping during a sinter for 20 min at 420 °C, for two different TSV dimensions. Using optical profilometry, in total ~ 4000 TSVs were measured, allowing detailed statistical analysis. Within one sample the Cu pumping values were found to be log normally distributed, implying an intrinsically large spread. Lower residual Cu pumping values were found in TSVs annealed at higher temperatures and for longer times, with the sinter conditions of 20 min at 420 °C confirmed as optimal post-plating anneal conditions. The larger TSVs showed more pumping in the average TSV, but at the tail of the distribution the Cu pumping behavior was the same as for the smaller TSVs. This implies that the impact of Cu pumping on BEOL reliability is identical for both sets of TSV dimensions, suggesting that the impact of Cu pumping on BEOL reliability is not necessarily reduced by reducing TSV dimensions.

Correlation between Cu microstructure and TSV Cu pumping

Cu pumping is the irreversible extrusion of Cu from Cu-filled through-silicon vias (TSVs) exposed to high temperatures during back-end of line (BEOL) processing. The distribution of Cu pumping values over the TSVs of a single wafer has a large intrinsic spread. As potential BEOL reliability issues due to Cu pumping will first occur at the highest pumping TSVs, they can be mitigated if the fundamental cause for this large intrinsic spread is known and under control. This paper describes a clear correlation between Cu pumping and TSV Cu microstructure based on the grain size at the top of 5×50 μm TSV, disregarding twin boundaries. For the mitigation of TSV Cu pumping the ideal microstructure was shown to consist of a single grain spanning the whole TSV cross section, bringing down the highest measured Cu pumping value from 248 nm to 73 nm. This effect was attributed to the absence of rapid diffusion paths and grain boundary sliding ability.

Highly reliable CMOS-integrated 11MPixel SiGe-based micro-mirror arrays for high-end industrial applications

In this paper we report for the first time on the fabrication of very reliable CMOS-integrated 10 cm2 11 MPixel SiGe-based micro-mirror arrays on top of 6 level metal CMOS wafers. The array, which is to be used as Spatial Light Modulator (SLM) for optical maskless lithography [1,2,3] consists of 8 mum x 8 mum pixels which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. The pixel density is almost double compared to the state-of-the-art [4]. A stable average cupping below 7 nm, an RMS roughness below 1 nm and long lifetime (>1012 cycles, no creep [5]) are demonstrated.

11-Megapixel CMOS-Integrated SiGe Micromirror Arrays for High-End Applications

In this paper, we report on the design, fabrication, packaging, and testing of very reliable CMOS-integrated 10-cm2 11-megapixel SiGe-based micromirror arrays on top of planarized six-level metal 0.18-¿m CMOS wafers. The array, which is to be used as a spatial light modulator (SLM) for optical maskless lithography, consists of 8 ¿m × 8 ¿m pixels, which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. Due to very stringent requirements on mounted-die flatness (< 0.01 mrad), the first level packaging of SLM die is done using specially designed SiC holders. To avoid trapped particles between the die and holder, which would jeopardize the flatness spec, special backside cleaning of the dies (less than or equal to one 0.8-¿m particle/cm2) is needed before mounting the SLM die on the holder. To enable this backside cleaning and to avoid front-side particles during dicing, handling, and wire bonding, a temporary waferor zero-level packaging cap, which can be placed and removed at room temperature, was developed. The dynamic white light interferometer measurements of packaged dies showed that 99.5% of the 123 648 mirrors tested are within the spec. In addition, a stable average cupping of below 7 nm, an rms roughness of below 1 nm, and a stable actuation of over 2.5 teracycles are demonstrated.

CMOS-integrated poly-SiGe cantilevers with read/write system for probe storage device

A poly-SiGe technology enabling a dense array of micro-cantilevers and tips on CMOS is demonstrated. Built from a dual-thickness structural layer, the cantilevers feature a very small initial bending and have a compliant torsional suspension with a stiffness of 3×10−10 Nm/rad. Sharp tips are formed in a low-temperature amorphous silicon layer by isotropic plasma etching. An electrical read/write system is formed by connecting the tip to the CMOS with a suspended platinum trace, running on top of the cantilever.

Ruthenium metallization for advanced interconnects

We demonstrate 10 nm half-pitch (HP) Ruthenium interconnects filled by atomic layer deposition (ALD). The resistivity and the cross-sectional area of Ruthenium interconnects were determined via the Matthiessens rule method. We find that the resistivity of Ru was rather independent of the cross-sectional area of the interconnect, increasing from 12 μΩcm for larger lines to 15-17 μΩcm for cross-sectional areas of 200-300 nm2. 10 nm HP Ru lines showed no electromigration failures at 5 MA/cm2 and 300°C during 1000 hours. Time-dependent dielectric breakdown measurements indicated that Ruthenium does not require a diffusion barrier on both dense and porous low-κ dielectrics.

Reliability Challenges Related to TSV Integration and 3-D Stacking

This article identifies four major reliability challenges related to TSV-based 3-D integrated circuits and their solutions that are being developed at imec.

Nondestructive Monitoring of Die Warpage in Encapsulated Chip Packages

We describe an X-ray diffraction imaging technique for nondestructive, in situ measurement of die warpage in encapsulated chip packages at acquisition speeds approaching real time. The results were validated on a series of samples with known inbuilt convex die warpage, and the measurement of wafer bow was compared with the results obtained by optical profilometry. We use the technique to demonstrate the impact of elevated temperature on a commercially sourced micro quad flat nonlead chip package and show that the strain becomes locked in at a temperature between 94 °C and 120 °C. Using synchrotron radiation at the Diamond Light Source, warpage maps for the entire 2.2 mm × 2.4 mm × 150-μm Si die were acquired in 50 s, and individual line scans in times as short as 500 ms.

Functionality, yield and reliability analysis of SiGe micro-mirrors using automated optical measurement techniques

This paper discusses optical systems for automatic, wafer or chip level measurements of metrology, functional yield and reliability of MEMS. The functionality of the systems is demonstrated on megapixel arrays of SiGe micro-mirrors. The back-bone of the systems is formed by existing commercial systems, but home-developed procedures and software were written to extend their functionality and applicability.

Thermal compression bonding of 20 μm pitch micro bumps with pre-applied underfill — Process and reliability

Thermal compression bonding (TCB) process in combination with a pre-applied underfill material has been developed and investigated for assembling 20 μm pitch Sn-based micro bumps. It is found bonding force has a profound impact on the joint formation behavior. A low bonding force produces bump joints with heavier underfill entrapment and incompletely reacted solder. A higher bonding force leads to more solder squeezing-out, leaving a thin and completely reacted inter-metallic compound (IMC) layer in the joints. Electrical measurement of the daisy chains on the as-bonded chips does not reveal any significant difference between the samples made with different bonding forces. The reliability of the two types of joints were further studied in two post-bonding tests, namely the resistance measurement of daisy chains at an elevated temperature and stack-level thermo-cycling test. Both tests show a better reliability performance from the bump joints with less underfill entrapment and completely reacted IMC layer.