Jonathan R. Ahlbin

Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits

Heavy-ion broad-beam experiments on a 130 nm CMOS technology have shown anomalously-short single-event transient pulse widths. 3-D TCAD mixed-mode modeling in 90 nm and 130 nm bulk CMOS has identified a mechanism for simultaneous charge collection on proximal circuit nodes interacting in a way as to truncate, or ¿quench,¿ a propagated voltage transient, effectively limiting the observed SET pulse widths at high LET. This quenching mechanism is described and analyzed.

Effect of Well and Substrate Potential Modulation on Single Event Pulse Shape in Deep Submicron CMOS

Simulations are used to characterize the single event transient current and voltage waveforms in deep submicron CMOS integrated circuits. Results indicate that the mechanism controlling the height and duration of the observed current plateau is the redistribution of the electrostatic potential in the substrate following a particle strike. Quantitative circuit and technology factors influencing the mechanism include restoring current, device sizing, and well and substrate doping.

Design Techniques to Reduce SET Pulse Widths in Deep-Submicron Combinational Logic

Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on the PMOS device. This difference is exploited to optimize transistor sizing and n-well contact layout for SET RHBD in combinational logic.

The Effect of Layout Topology on Single-Event Transient Pulse Quenching in a 65 nm Bulk CMOS Process

Heavy-ion microbeam and broadbeam data are presented for a 65 nm bulk CMOS process showing the existence of pulse quenching at normal and angular incidence for designs where the pMOS transistors are in common n-wells or isolated in separate n-wells. Experimental data and simulations show that pulse quenching is more prevalent in the common n-well design than the separate n-well design, leading to significantly reduced SET pulsewidths and SET cross-section in the common n-well design.

Layout Technique for Single-Event Transient Mitigation via Pulse Quenching

A layout technique that exploits single-event transient pulse quenching to mitigate transients in combinational logic is presented. TCAD simulations show as much as 60% reduction in sensitive area and 70% reduction in pulse width for some logic cells.

Scaling Trends in SET Pulse Widths in Sub-100 nm Bulk CMOS Processes

Digital single-event transient (SET) measurements in a bulk 65-nm process are compared to transients measured in 130-nm and 90-nm processes. The measured SET widths are shorter in a 65-nm test circuit than SETs measured in similar 90-nm and 130-nm circuits, but, when the factors affecting the SET width measurements (in particular pulse broadening and the parasitic bipolar effect) are considered, the actual SET width trends are found to be more complex. The differences in the SET widths between test circuits can be attributed in part to differences in n-well contact area. These results help explain some of the inconsistencies in SET measurements presented by various researchers over the past few years.

Mitigation Techniques for Single-Event-Induced Charge Sharing in a 90-nm Bulk CMOS Process

In this paper, mitigation techniques to reduce the increased SEU cross section associated with charge sharing in a 90-nm dual-interlocked-cell latch are proposed. The increased error cross section is caused by heavy-ion angular strikes depending on the direction of the ion strike, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal spacing as a mitigation technique shows an order of magnitude decrease on upset cross section as compared to a conventional layout, and the use of guard-rings show no noticeable effect on upset cross section.

SEU Prediction From SET Modeling Using Multi-Node Collection in Bulk Transistors and SRAMs Down to the 65 nm Technology Node

A new methodology of prediction for SEU is proposed based on SET modeling. The modeling of multi-node charge collection is performed using the ADDICT model for predicting single event transients and upsets in bulk transistors and SRAMs down to 65 nm. The predicted single event upset cross sections agree well with experimental data for SRAMs.

Effect of Transistor Density and Charge Sharing on Single-Event Transients in 90-nm Bulk CMOS

Heavy-ion experiments on spatially isolated inverters and densely populated inverters demonstrate the effects of transistor density on single-event (SE) transients in bulk CMOS. Increased transistor density reduces SE cross section dramatically while having little impact on transient pulse width.

Independent Measurement of SET Pulse Widths From N-Hits and P-Hits in 65-nm CMOS

A novel circuit design for separating single-event transients due to N-hits and P-hits is described. Measurement results obtained from a 65 nm technology using heavy-ions show different dominant mechanisms for charge collection for P-hits and N-hits. The data collected represent the first such separation of SET pulse widths for 65 nm bulk CMOS technology. For low LET particles, N-hit transients are longer, but for high LET particles, P-hit transients are longer. N-well depth and the parasitic bipolar effect are shown to be the most important parameters affecting transient pulse widths.