N. M. Atkinson

Layout Technique for Single-Event Transient Mitigation via Pulse Quenching

A layout technique that exploits single-event transient pulse quenching to mitigate transients in combinational logic is presented. TCAD simulations show as much as 60% reduction in sensitive area and 70% reduction in pulse width for some logic cells.

Effect of Transistor Density and Charge Sharing on Single-Event Transients in 90-nm Bulk CMOS

Heavy-ion experiments on spatially isolated inverters and densely populated inverters demonstrate the effects of transistor density on single-event (SE) transients in bulk CMOS. Increased transistor density reduces SE cross section dramatically while having little impact on transient pulse width.

Effect of Multiple-Transistor Charge Collection on Single-Event Transient Pulse Widths

Heavy-ion data from a 130-nm bulk CMOS process shows a counterproductive result in using a common single-event charge collection mitigation technique. Guard bands, which are well contacts that surround individual transistors, can reduce single-event pulsewidths for normal strikes, but increase them for angled strikes. Calibrated 3-D TCAD mixed-mode modeling has identified a multiple-transistor charge collection mechanism that explains the experimental data, namely that angled strikes result in charge collection in the normally ON device that increases the restoring current on the struck device.

Impact of Well Structure on Single-Event Well Potential Modulation in Bulk CMOS

Perturbations in N-well potential have been shown to strongly affect the charge collection, charge sharing, and parasitic bipolar transistor characteristics. In this paper, temporal and spatial characteristics of the well-potential modulation are characterized through 3-D TCAD simulations. Effects of well-contact layout, ion energy, and technology process parameters for a 90-nm bulk CMOS process are investigated.

On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology

Direct observation of fast-transient single event signatures often involves considerable uncertainty due to the limitations of monitoring circuitry. A built-in-self-test circuit for the measurement of single-event transients (SET) has been implemented in a 45 nm partially depleted silicon-on-insulator technology that allows for the extraction of measurement-induced uncertainty. SET pulse width data from heavy-ion experiments are provided and compared to technology computer aided design simulations. A method for compensating for the measurement bias and skew is provided.

Differential Charge Cancellation (DCC) Layout as an RHBD Technique for Bulk CMOS Differential Circuit Design

A novel RHBD technique utilizing charge sharing to mitigate single-event voltage transients in differential circuits is demonstrated experimentally. Differential charge cancellation (DCC) layout leverages the inherent common-mode rejection of differential circuits to mitigate voltage transients induced by ion strikes. A simple layout variation transforms normally single-ended error signals into common-mode signals that are mitigated by the differential signal path. This layout change maintains the matching achieved via a standard common-centroid layout but incurs negligible area penalty.

Influence of N-Well Contact Area on the Pulse Width of Single-Event Transients

Heavy-ion broadbeam results from a 90 nm process are presented for five inverter chains with varying n-well contact schemes. Results show that inverters with the smallest percentage of n-well contact area within an n-well produced the longest and most frequent single-event transients (SETs). As the percentage of n-well area contacted increases above 2%, the pulse width and number of SETs levels-off. A result indicating an optimized percentage of n-well area contacted can be calculated that minimizes the pulse width and number of SETs in a digital circuit.

RHBD Bias Circuits Utilizing Sensitive Node Active Charge Cancellation

A novel radiation-hardened-by-design (RHBD) technique that utilizes charge sharing to mitigate single-event voltage transients is employed to harden bias circuits. Sensitive node active charge cancellation (SNACC) compensates for injected charge at critical nodes in analog and mixed-signal circuits by combining layout techniques to enhance charge sharing with additional current mirror circuitry. The SNACC technique is verified with a bootstrap current source using simulations in a 90-nm CMOS process. Reductions of approximately 66% in transient amplitude and 62% in transient duration are observed for 60-degree single-event strikes with an LET of 40 MeV*cm2/mg. The SNACC technique can be extended to protect multiple sensitive nodes (M-SNACC). M-SNACC is used to harden the bias circuit of a complementary folded cascode operational amplifier, providing a significant reduction in single-event vulnerability for a 8-bit digital-to-analog converter.

Effect of Device Variants in 32 nm and 45 nm SOI on SET Pulse Distributions

Single-Event Transient (SET) pulse widths were obtained from the heavy-ion irradiation of inverters designed in 32 nm and 45 nm silicon-on-insulator (SOI). The effects of threshold voltage and body contact are shown to significantly impact the SET response of advanced SOI technologies. Also, the reverse cumulative distribution is extracted from the count distribution for several targets and is shown to be a useful aid in selecting the temporal filtering for radiation-hardened circuitry.

RHBD Technique for Single-Event Charge Cancellation in Folded-Cascode Amplifiers

A novel RHBD technique that exploits charge sharing is implemented in the single-ended gain stage of a folded-cascode operational amplifier to mitigate single-event transients (SETs). The efficacy of the technique is demonstrated via two-photon laser experiments. Using settling time as the primary metric for SET severity, the proposed layout technique achieves sensitive area reductions ranging from 41% to 95% with an overall area penalty of less than 1%.