Yu Gyun Shin

Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor (RCAT) and tungsten gate

In this work, HfSiON gate dielectric is integrated for the first time in dual gate oxide of DRAM with recess channel arrary transistor (RCAT) and W/poly-Si gate for the development of sub-60nm DRAM technology. No degradation of cell transistor characteristics was observed with HfSiON gate dielectric. In peripheral transistors, excellent sub-threshold swings and driving current of 515 /spl mu/A//spl mu/m and 216 /spl mu/A//spl mu/m for nMOS and pMOS, respectively, at V/sub dd/=1.8V and I/sub off/=20/spl mu/A//spl mu/m were obtained. Compared to surface channel pMOSFET, lower V/sub th/ was achieved in buried channel pMOSFET due to fermi-level pinning. Negligible increase of gate leakage current during post annealing up to 950/spl deg/C for 30min is shown the excellent thermal stability of HfSiON dielectric.

An optimized densification of the filled oxide for quarter micron shallow trench isolation (STI)

Densification methods using H/sub 2/O and N/sub 2/ ambient annealing of the filled CVD oxide for quarter micron STI are compared. Although the H/sub 2/O ambient oxidation is more effective in terms of the resistance against the HF etching, volume expansion by the trench sidewall oxidation generates a large amount of stress in the narrow isolation region. However, an N/sub 2/ gas ambient annealing at high temperature shows a low stress and a low HF etch rate which enable us to fabricate the stable quarter micron STI.

Correlation between gate oxide reliability and the profile of the trench top corner in Shallow Trench Isolation (STI)

In order to develop a Shallow Trench Isolation (STI) which does not have trench corner induced degradation of the gate oxide, its integrities were evaluated with rounded, non-rounded top corner, and an addition of CVD SiO/sub 2/ spacer. In the experiment, we found that the rounded and SiO/sub 2/ spacered STI showed the best result meaning no harmful influence of the corner to the gate oxide integrity. Also, etch-back processes of the filled CVD SiO/sub 2/ were modified to eliminate the degradation of the gate oxide by a stress concentration at top corner kinks.

A 22-nm damascene-gate MOSFET fabrication with 0.9-nm EOT and local channel implantation

We introduce a novel CMOS transistor fabrication technique using damascene gate with local channel implantation (LCI). This transistor has a benefit to reduce the resistance of source/drain extension (SDE) localizing the severe blanket channel implantation under the channel only. It can reduce the junction capacitance as well. This process technology is reliable for the formation of channel length down to 22 nm with smooth gate line edge roughness. Some unique processes for the small transistor fabrication are also introduced. The 22-nm nMOSFET with 0.9 nm RTO is achieved with the drive current of 930 /spl mu/A//spl mu/m for the off-current of 100 nA//spl mu/m at 1.0 V. Hot carrier reliability exceeding 10 years for 1.0 V operation is also obtained.

Ultra Shallow Junction Formation Using Plasma Doping and Laser Annealing for Sub-65 nm Technology Nodes

Plasma doping and laser annealing are successfully integrated into the conventional p-metal–oxide–silicon field effect transistor (PMOSFET) process to form ultra shallow junction (USJ). Comparing with the conventional combination of ion implantations and rapid thermal annealing (RTA), junction depth (XJ) and sheet resistance (RS) are reduced. Also, significant improvement of the short channel effects without the degradation of on-current is observed.

The Effect of Stress on Solid-Phase Epitaxial Regrowth in As+-Implanted Two-Dimensional Amorphized Si

The effect of stress induced by a chemical-vapor-deposited (CVD) SiO2 film on the solid-phase epitaxial (SPE) regrowth in As+-implanted, two-dimensional amorphized Si has been studied. Trench structures were used to form the two-dimensional amorphous layer and to induce the stress in the Si substrate. As+ implantation at an energy of 80 keV with a dose of 3×1015/cm2 amorphized the silicon surface and produced a curved amorphous/crystalline (a/c) interface under the bottom corner of the trenches. At the trenches filled with the high-tensile-stress CVD SiO2 film, the regrowth of the amorphous Si layers was retarded and a notch remained in the a/c interface immediately under the bottom corner of the trench after annealing at 500°C for 4 h. The regrowth retardation and the remaining notch were explained by the effect of the stress induced by the CVD SiO2 film on the activation barrier of the SPE regrowth.

Improved Cell Performance for sub-50 nm DRAM with Manufacturable Bulk FinFET Structure

FinFET, the milestone for sub-50 nm DRAM cell transistor has been successfully demonstrated by a unique fabricating method with novel concept. We obtained a core solution of front-end-of-line process and structure, focusing on short channel behavior, off-state leakage, and saturation current. We have developed the scheme that is able to suppress off-state leakage current below 1 fA/cell with p+ poly-Si gate. We have also examined mobility and parasitic engineering techniques to maximize the cell performance (DeltaIon > 48 %). In conclusion, we propose the effective guideline for highly manufacturable FinFET for DRAM application at the sub-50 nm node.

A new ruler on the storage market: 3D-NAND flash for high-density memory and its technology evolutions and challenges on the future

Scaling limitations in planar-NAND cell are discussed, including the depletion of floating gate and anomalous programming behavior. It is inevitable to have a paradigm shift to 3D-NAND due to numerous scaling limitations of planar NAND. However, the process complexity also increases in 3D-NAND as the mold height goes up in an exponential trend. Thus, scaling down of mold pitch is required, which degrades the cell characteristics. COP (Cell over Peripheral) 3D-NAND architecture has been developed as an area-scaling technology. CSL (Common-Source Line) junction leakage and p+ junction leakage at peripheral transistors have been improved by increasing the grain size and the thickness of barrier metal, respectively.

Effects of Post-Deposition Annealing on the Electrical Properties of HfSiO Films Grown by Atomic Layer Deposition

Post-deposition annealing was investigated for hafnium silicate films deposited on Si substrates by atomic layer deposition. Annealing in NH3 at 750°C incorporated 13 At.% nitrogen in hafnium silicate, and hysteresis significantly depended on film thickness. In contrast, annealing in N2 at 950°C suppressed hysteresis and its dependence on the film thickness. In addition, effective mobility and positive bias temperature instability were improved by N2 annealing of as-deposited hafnium silicate films. Finally, additional N2 annealing following NH3 annealing was effective to obtain highly dense hafnium silicate films with good mobility and optimized nitrogen incorporation.

Integration of Sub-melt Laser Annealing on Metal Gate CMOS Devices for Sub 50 nm Node DRAM

We report on the integration of sub-melt laser spike annealing (LSA) on W-gate stacked DRAM. We applied the LSA as a reactivation in back-end processes to comply with the considerable metal-pattern effects and strong DRAM thermal-budget. Improvements in drive currents of peripheral transistors (4 %/14 % for n/p-FETs) are achieved by using the LSA without incurring short channel effect (SCE) while minimizing pattern effects of metal gate. DRAM cell transistors also show improvements in drive current, junction leakage, and GIDL (gate-induced drain leakage) without laser-induced local defects and reliability degradation