S.O. Park

Electrical observations of filamentary conductions for the resistive memory switching in NiO films

Experimental results on the bistable resistive memory switching in submicron sized NiO memory cells are presented. By using a current-bias method, intermediate resistance states and anomalous resistance fluctuations between resistance states are observed during the resistive transition from high resistance state to low resistance state. They are interpreted to be associated with filamentary conducting paths with their formation and rupture for the memory switching origin in NiO. The experimental results are discussed on the basis of filamentary conductions in consideration of local Joule heating effect.

A novel cell technology using N-doped GeSbTe films for phase change RAM

The Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST) thin film is well known to play a critical role in PRAM (Phase Change Random Access Memory). Through device simulation, we found that high-resistive GST is indispensable to minimize the writing current of PRAM. For the first time, we tried to increase the GST resistivity by doping nitrogen. Doping nitrogen to GST successfully reduced writing current. Also, the cell endurance has been enhanced with grain growth suppression effect of dopant nitrogen.

Full integration and reliability evaluation of phase-change RAM based on 0.24 /spl mu/m-CMOS technologies

We have fully integrated a nonvolatile random access memory by successfully incorporating a reversibly phase-changeable chalcogenide memory element with MOS transistor. As well as basic characteristics of the memory operation, we have also observed reliable performances of the device on hot temperature operation, endurance against repetitive phase transition, writing imprint, reading disturbance and data retention.

Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb

We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12/spl mu/m-CMOS technologies. Ge/sub 2/Sb/sub 2/Te /sub 5/ was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.

Improvement of resistive memory switching in NiO using IrO2

For the development of resistive memory devices using NiO, improvements of several memory switching properties are required. In NiO memory cells with noble metal electrodes, broad dispersions of memory switching parameters are generally observed with continuous memory switchings. We report the improvements in minimizing the dispersions of all memory switching parameters using thin IrO2 layers between NiO and electrodes. The role of thin IrO2 layers on NiO growth and memory switching stabilization are discussed.

An edge contact type cell for Phase Change RAM featuring very low power consumption

In this paper, the Phase Change Random Access Memory (PRAM, also known as Ovonic Unified Memory-OUM) cell, which has an extremely small and reproducible contact area and improved thermal environment, was fabricated and electrically characterized. The memory cell successfully operates with 30 ns pulses of 0.20 mA for RESET (high resistive) state and 0.13 mA for SET (low resistive) state. This is the best record of the published data.

Highly Scalable Phase Change Memory with CVD GeSbTe for Sub 50nm Generation

first present a PRAM with confinement of chemically vapor deposited GeSbTe (CVD GST) within high aspect ratio 50 nm contact for sub 50 nm generation PRAMs. By adopting confined GST, we were able to reduce the reset current below ~260 muA and thermally stable CVD Ge2Sb2Te5 compound having hexagonal phase was uniformly filled in a contact while maintaining constant composition along with 150 nm depth. Our results indicate that the confined cell structure of 50 nm contact is applicable to PRAM device below 50 nm design rule due to small GST size based on small contact and direct top electrode contact, reduced reset current, minimized etch damage, and low thermal disturbance effect.

Integration and electrical properties of diffusion barrier for high density ferroelectric memory

A reliable Ir diffusion barrier was prepared on polysilicon plugged substrate with a contact size of 0.6 μm. Using a Ti adhesion layer and stress-relief process, it was possible to integrate the Ir barrier into a high density 4 Mb ferroelectric random access memory device. After heat treating sol-gel derived Pb(Zr1−xTix)O3 (PZT) films at 700 °C, the Ir barrier contact displayed an ohmic behavior and showed a low resistance of 130 Ω per contact in 1k serial contact array. The PZT films on Pt/IrO2/Ir poly-plugged substrate exhibited excellent ferroelectric properties such as remnant polarization and coercive voltage of 25 μC/cm2 and 1.15 V, respectively. Auger depth profile and transmission electron microscopy analyses confirmed that no appreciable oxidation was formed between the Ir barrier and the polysilicon plug.

Phase-change chalcogenide nonvolatile RAM completely based on CMOS technology

We have integrated a phase-change chalcogenide random access memory, completely based on 0.24 /spl mu/m-CMOS technologies. A twin cell and BL clamping circuits are introduced to enlarge fabrication tolerance and to reduce cell perturbation during reading operation. To draw back current as much as possible, Co salicidation is also applied to transistor formation. By constructing a simple cell structure with Ge/sub 2/Sb/sub 2/Te/sub 5/, we have observed reliable phase-transitions by driving current through MOS transistors. With 100 ns-writing pulses of 2 mA for RESET and 0.6 mA for SET, the device operates successfully with a considerable sensing signal at reading voltage of as low as 0.2 V.

One dimensional conversion of color temperature in perceived illumination

This paper proposes a one-dimensional conversion method of color temperature in perceived illumination. It also presents the design and implementation of the method. The proposed method is verified using the Xilinx Virtex FPGA XCV 2000-6BG560. This method is demonstrated experimentally for color temperatures in the range of 3000 K to 25000 K. This can be applied into special effect for multimedia applications.