Jose Ignacio Garate
University of the Basque Country
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Featured researches published by Jose Ignacio Garate.
IEEE Transactions on Power Electronics | 2017
Oier Onederra; Iñigo Kortabarria; Iñigo Martínez de Alegría; Jon Andreu; Jose Ignacio Garate
Loss reduction in converters is one of main targets in power electronics to obtain higher efficiency and lower thermal stress, which can enhance the lifetime of devices. This paper presents a variable switching frequency technique for switching loss reduction in a three-phase voltage source inverter, obtaining similar output current quality as that of a space vector pulse width modulation (SVPWM) algorithm. This type of optimization has not been applied for a three-phase system before. Simulation and experimental results are also shown. The output current ripple rms value of three-phase SVPWM is used as the optimization constraint. Results of the optimization of the switching losses with quality constraints in the switching frequency as the variable are presented for different load angles and compared with classical SVPWM. Experimental results show that this technique can save up to nearly
IEEE Transactions on Smart Grid | 2015
J. A. Araujo; Jesús Lázaro; Armando Astarloa; Aitzol Zuloaga; Jose Ignacio Garate
19\%
international symposium on industrial electronics | 2006
Jose Ignacio Garate; J.M. de Diego; S.P. Perea
in switching losses with similar total harmonic distortion of the output current, concluding that converter losses are reduced without reducing output current quality.
international conference on industrial technology | 2006
Jose Miguel de Diego; Jose Ignacio Garate
Critical systems require zero recovery time when a failure occurs in a communications network. The soon to be implemented standard IEC 62439-3 defines the only two protocols, parallel redundancy protocol and high-availability seamless redundancy, which fulfill this requirement and ensure no frame loss in the presence of an error. These protocols also provide a hot-plugging capability, which allows elements to be added to or removed from the network without interrupting communications and the operation of the plant. The electricity sector has adopted these for power utility automation in the recently published IEC 61850-90-4. The challenge is to obtain an efficient approach for use in electronic devices, capable of managing the characteristic duplicates, and circulating frames of these protocols, coupled with agile architectures capable of dealing with real-time processing requirements, fast switching times, high throughput, and deterministic behavior. The main contribution of this paper is the in-depth analysis it makes of network parameters imposed by the application of the protocols to power utility automation, and the proposition of a frame management system based on a segmented memory system that improves frame detecting time and uses the smallest memory required in order to resolve all the issues dealt with.
conference of the industrial electronics society | 2006
Jose Ignacio Garate; Jose Miguel de Diego; Maite Sierra
This paper proposes a more precise way of radiofrequency output power control and sensing for mobile base station transmitters without increasing the complexity of the AGC of their power amplifier in order to overcome the design adjustment problems and the production ones. The solution presented is based on measuring both the output power RF and the current consumption of the PA. The solution has been tested on commercial GSM triple-band fixed cellular terminals and prototypes of 3G power amplifiers.
conference of the industrial electronics society | 2016
Asier Matallana; Jon Andreu; Jose Ignacio Garate; Iker Aretxabaleta; Estefanía Planas
The present paper introduces a power supply system for Machine to Machine Modules and Fixed Cellular Terminals with discontinuous current consumption. The architecture proposed tries to solve the input high current peaks derived from the discontinuous current consumption of the PA. The final solution decreases the voltage supply ripple and current peak applied to the battery. The document also describes the problem and shows a practical implementation of the solution proposed.
conference of the industrial electronics society | 2008
Mª Teresa Sierra; Jaime Jimenez; Unai Bidarte; Jose Ignacio Garate; Aitzol Zuloaga
The present paper analyzes the problems derived of high level discontinuous current consumption of electronic devices powered with batteries. The study is focus in the particularly in the case of wireless and cellular terminals where the effects in their functionality are severe. It is also introduced the tradeoffs of the different technical solutions available to overcome the problems derived from discontinuous current consumption
international symposium on industrial electronics | 2017
Asier Matallana; Jon Andreu; Jose Ignacio Garate; Iñigo Martínez de Alegría; Iñigo Kortabarria
In some power electronic applications, with high current and voltage ranges, discrete devices are not enough unless parallelization techniques are employed. IGBTs are one of the most common and widespread power electronic semiconductors, to make a parallel design with them, either as a discrete devices, dies, individual cells or power modules, it is necessary to know their static and dynamic behaviour. Besides, operation temperature, device parameter tolerances, driver circuit and power layout, as well as different parasitic inductance also affect its performance. The objective of this article is to show and model how all the aforementioned parameters affect the behaviour and performance of a parallelized IGBT, and highlight the design keys for a successful parallelized design.
ieee international conference on compatibility power electronics and power engineering | 2017
Itxaso Aranzabal; I. Martínez de Alegría; Jose Ignacio Garate; Jon Andreu; N. Delmonte
The present paper provides an introduction to the concepts and hints used to layout PCBs (printed circuit boards) with good SI (signal integrity) and EMI (electromagnetic interference) control when designing RF (radio frequency), analog and digital electronic circuits, within the same PCB. This document also analyses the problem of getting good SI and EMI performance in dense populated PCBs with mixed technologies whenever interactions between technologies could not be avoided.
technologies applied to electronics teaching | 2014
Gerardo Aranguren; Luis A. López-Nozal; Jose Ignacio Garate
Power electronic applications need high voltage and current ranges which are impossible to obtain with discrete devices. Parallelization technique is a solution to increase power converter current capacity. Current distribution problems may reduce device lifetime and cause converter malfunction. Parallelization requires a total control of circuit parasitic elements which depend on layout physical materials and dimensions. The objective of this article is to show, by electromagnetic (EM) model simulations, layout non ideal effects for power circuits, in order to understand and control circuit stray elements, especially parasitic inductances, and current distributions.