Ju-Seop Park

Stack friendly all-oxide 3D RRAM using GaInZnO peripheral TFT realized over glass substrates

This paper reports on new concept consisting of all-oxide-based device component for future high density non-volatile data storage with stackable structure. We demonstrate a GaInZnO (GIZO) thin film transistors (TFTs) integrated with 1D (CuO/InZnO)-1R (NiO) (one diode-one resistor) structure oxide memory node element. RRAM (Resistance Random Access Memory) has provided advantages in fabrication which have made these works possible. Therefore we also suggest methods and techniques for improving the distribution in bi-stable resistance characteristics of the NiO memory node. In order to fabricate stack structures, all device fabrication steps must be possible at low temperatures. The benefits provided by low temperature processes are demonstrated by our devices fabricated over glass substrates. Our paper shows the device characteristics of each individual component as well as the characteristics of combined select transistor with 1D-1R cell. XPS analysis of NiO RRAM resistance layer deposited by ALD confirms similar conclusions to previous reports of the importance of metallic Ni content in sputtered NiO for bistable resistance switching. Also we herein propose a generalized stacked-memory structure to minimize on-chip real estate to maximize integrated density.

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

A higher performance DRAM is required by the market due to the increasing of bandwidth of networks and the rise of high-capacity multimedia content. DDR4 SDRAM is the next-generation memory that meets these demands in computing and server systems. In comparison with current DDR3 memory, the major changes are supply voltage reduction to 1.2V, pseudo open drain I/O interface, and data rate increase from 1.6 to 3.2Gb/s. To achieve high performance at low supply voltage and reduce power consumption, this work introduces new functions and describes their implementation. Data bus inversion (DBI) is employed for high-speed transactions to reduce power consumption of I/O and SSN noise. Dual-error detection, which adopts cyclic redundancy check (CRC) for DQ, and command address (CA) parity is designed to guarantee reliable transmission. GDDR5 memory also has DBI and CRC functions [1], but in this work, these schemes are implemented in a way that reduces area overhead and timing penalty. Besides these error-check functions, an enhanced gain buffer and a PVT-tolerant fetch scheme improve basic receiving ability. To meet the output jitter requirements of DDR4 SDRAM, the type of delay line for DLL is selected at initial stage according to data rate.

Simultaneously formed storage node contact and metal contact cell (SSMC) for 1 Gb DRAM and beyond

Simultaneously formed Storage node contact and Metal contact Cell (SSMC) was investigated and developed with 0.18 /spl mu/m advanced KrF lithography as a promising candidate for the cell structure of 1 Gb DRAM and beyond, such as 4 Gb and 16 Gb DRAMs. SSMC can provide fast and reliable memory cell operation by reducing parasitic resistance between memory cell storage node and access transistor. Also SSMC can reduce the processing steps compared to the conventional COB (Capacitor Over Bit line) cell by forming storage node contact holes and metal contact hole at the same time. Furthermore, it is found that SSMC has many other advantages in terms of process margin, and wide application, for example in EML (embedded memory logic). Thus, SSMC is a promising cell structure for 1 Gb DRAM and beyond.

Considering physical mechanisms and geometry dependencies in 14nm FinFET circuit aging and product validations

We report the extensive 14nm FinFET reliability characterization work and provide physical mechanisms and geometry dependencies. BTI, HCI variability related to #of Fin used in design along with self-heat considerations are critical for product design and qualifications. We show that along with increased AFs and optimized product HTOL stress conditions, 5-10x more efficiency in time has been achieved. In addition, external mechanical strain on Fin reliability will be discussed.

Isolation merged bit line cell (IMBC) for 1 Gb DRAM and beyond

The Isolation-Merged Bit Line Cell (IMBC) structure was investigated with 0.20 /spl mu/m advanced Deep UV lithography as a candidate cell structure for 1 Gb DRAM and beyond. Better photo margin owing to the improvement of bit-line and global topology, easy formation of cell capacitor, simple process and better process margin were accomplished in IMBC. The electrical characteristics of IMBC was comparable to that of the conventional Capacitor Over Bit line (COB) cell. Moreover, the bit line coupling noise was significantly reduced in IMBC compared with COB. Thus, IMBC is a promising cell structure for 1 Gb DRAM and beyond.