Julian Bravin

Thin WLFO and based WLSiP enabling WL3D, realized using Temporary Reconstituted Panel Bonding Technology

The interest in FOWLP as new flexible packaging technology platform is continuously increasing. High volume capability is proven for configurations with single die (WLFO), multi-die side-by-side, partially with discrete passives integration (WLMCM and WLSiP), both with single sided single and multiple RDL layers. The next step to achieve higher integration density, e.g. for mobile and IoT applications, is to go in the third dimension (WL3D/WLPoP) with total package thickness below 1mm, targeting 0.8mm and even less in the next development step. High design flexibility, superior performance and small form-factor in x and y, but even more important in z-dimension, are the essential packaging characteristics required for this type of smart system integration. The eWLB based WLFO technology platform of NANIUM promises to deliver all of those requirements. While previous generations of WLFO packages only consisted of one plane of single or multiple RDL layers (frontside RDL at BGA side), recent evolutions enab...

Critical Process Parameters And Failure Analysis For Temporary Bonded Wafer Stacks

Temporary bonding is a ley process for almost any 3D integration scheme. It offers not only more stability during the thinning process but also allows handling for backside processing of thin wafers like interposers during subsequent process steps [1–2]. Although the temporary bonding technology is already used in high volume manufacturing and has proven high yield process, nevertheless, some limitation appears for some specific applications [3-4-5]. One critical failure origin is delamination, which can lead to wafer breakage and therefore yield loss. This separation of the device wafer and the carrier wafer typically occurs when the temporary bonded wafer stack (device wafer, carrier wafer and temporary bonding adhesive in between) experiences further processing done under high temperature and low vacuum like PECVD deposition. Further insight into processing parameters and a better understanding of the key contributing factors as well as its dependencies help to prevent this failure. To investigate the ...

Temporary bonding on the move towards high volume: A status update on cost-of-ownership

The ability to process thin wafers with thicknesses of 20-50um on front- and back side is a key technology for 3D stacked ICs (3Ds-IC). The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld consumer devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. Consensus has developed on the use of temporary bonding and debonding technology as the solution of choice for reliably handling thin wafers through back side processing steps. Temporary bonding and debonding comprises several processes for which yield is essential, as costly fully functional device wafers are being processed. The temporary bonding process yield has a major impact on the overall Cost of Ownership (CoO). On the other hand, throughput of the individual process steps like spin coating, bonding, cure, debonding and cleaning processes is the second determining factor for improved CoO. This paper should provide in depth understanding of CoO contributors to temporary bonding and debonding. Focus is put on the cost sensitivity of the major influencing contributor to temporary bond as well as debonding.

Versatile thin wafer stacking technology for monolithic integration of temporary bonded thin wafers

This paper will focus on recent results for wafer stacking of temporary bonded wafers for the integration in a monolithic device process. For ease of process integration, this process enables the face-to-back stacking of several device layers. Plasma activated fusion bonding could be shown to be an enabling step to lower annealing temperatures into a CMOS compatible range. Furthermore, plasma activation enables to use thermoplastic adhesives. Two types of test vehicles have been fabricated, showing on the one hand a successful stacking of a 11μm thin device wafer onto another thick substrate wafers. On the other hand, a triple stack of thick substrate wafer and two 20μm thin devices is shown as well. Bonding results have been measured using state-of-the-art measurement techniques, such as infrared scanning, scanning acoustic microscopy and scanning white light interferometry, to detect interface defects, bond integrity and temporary adhesive properties, respectively.

An innovative and low cost Bi-layer method for temporary bonding

The purpose of this work was to demonstrate the compatibility of Dow Cornings temporary bonding solution with EVGs 850XT universal temporary bonding and debonding platform. The proposed process made use of well-known processing steps and processing modules like spin coating. The process consisted of a release layer (Dow Corning® WL-3001 Bonding Release) and an adhesive layer (Dow Corning® WL-4050 or WL-4030 Bonding Adhesive) using an EVG® 850TB - 300 mm XT frame. Both layers of material were applied by spin coating on the device wafer side. In the frame of this study, silicon carriers were used. Bonding was performed under vacuum at room temperature. A post bonding bake step was applied using a hotplate. After subsequent backside processing steps, the room temperature debonding was performed.