Thomas Uhrmann

Silicon-based wafer-level packaging for cost reduction of high brightness LEDs

High brightness LEDs (HB-LEDs) carry a high prospect for general lighting applications. Competing with the cost/performance ratio of current light sources demands an increase of the overall efficiency as well as the reduction of the device cost. Since packaging accounts for 30%–50% of the cost of HB-LED manufacturing, moving from die-level to wafer-level processes is one likely potential solution for reducing cost per lumen. Silicon-based wafer-level-packaging (WLP), using the established processing technology of the MEMS and IC industry, offers high fabrication reliability, high yield and the direct integration of the driver IC in the package. The already small form factor of WLP can be further reduced using Through-Silicon-Vias (TSV), increasing the maximum amount of chips per wafer. Silicon WLP also offers superior thermal management, with the high thermal conductance of silicon. Redistributing LED dies on silicon wafer submounts, with metal bonding and copper TSVs, further improves the heat conductance away from the active region of the chip, resulting in increased device performance. Wafer-level optics can further improve performance and reduce packaging costs.

Recent progress in thin wafer processing

The ability to process thin wafers with thicknesses of 20-50um on front- and backside is a key technology for 3D IC. The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. The silicon real estate consumed by the TSVs has to be minimized in order that the final device provides a performance advantage compared to traditional 2D devices. The only way to reduce area consumption by the TSVs is to reduce their diameter. For a given wafer thickness the reduction of TSV diameter increases the TSV aspect ratio. Consensus has developed on the use of Temporary Bonding / Debonding Technology as the solution of choice for reliably handling thin wafers through backside processing steps. While the majority of the device manufacturing steps on the front side of the wafer will be completed with the wafer still at full thickness, it will be temporarily mounted onto a carrier before thinning and processing of the features on its backside. Once the wafer reaches the temporary bonding step, it already represents a significant value, as it has already gone through numerous processing steps. For this reason, inspection of wafers prior to non-reworkable process steps is of great interest. Within the context of Temporary Bonding this consideration calls for inline metrology that allows for detection of excursions of the temporary bonding process in terms of adhesive thickness, thickness uniformity as well as bonding voids prior to thinning of the product wafer. This paper introduces a novel metrology solution capable of detecting all quality relevant parameters of temporarily bonded stacks in a single measurement cycle using an Infrared (IR) based measurement principle. Thanks to the IR based measurement principle, the metrology solution is compatible with both silicon and glass carriers. The system design has been developed with the inline metrology task in mind. This has led to a unique system design concept that enables scanning of wafers at a throughput rate sufficient to enable 100% inspection of all bonded wafers inline in the Temporary Bonding system. Both, current generation temporary bonding system throughputs and future high volume production system throughputs as required by the industry for cost effective manufacturing of 3D stacked devices were taken into account as basic specifications for the newly developed metrology solution. Sophisticated software algorithms allow for making pass/ fail decisions for the bonded stacks and triggering further inspection, processing and / or rework. Actual metrology results achieved with this novel system will be presented and discussed. In terms of adhesive total thickness variation (TTV) of bonded wafers, currently achieved performance values for postbond TTV will be reviewed in light of roadmaps as required by high volume production customers.

Monolithic IC integration key alignment aspects for high process yield

Lithographic scaling has been the main growth driver to follow Moores law of cost reduction and performance increase for several decades. However, the 22nm node appears to be a game changer, where other core processes besides lithography have to be taken into account. Monolithic integration is one solution, where lithographic scaling is replaced by integration in vertical direction. Stacking and electrically contacting several semiconductor layers is challenging, as multiple unit processes have to be solved and put together. One of the key processes for monolithic integration is aligned wafer-to-wafer bonding. Besides optimization of the alignment accuracy, particle cleaning or plasma activation, earlier processing steps have important influence to a high yield processing of monolithic integrated circuits.

Influencing factors in high precision fusion wafer bonding for monolithic integration

Both fusion and hybrid wafer bonding are enabling increasing integration density as well as advanced device integration strategies. In any case, wafer-to-wafer overlay accuracy is the most critical factor for successful integration in 3D stacked devices. Despite alignment of both wafers is of major impact for the post-bond overlay accuracy, initiation and control of the bond wave between both substrate wafers the essential. During contacting device wafer surfaces, wafer stress as well as bow is influencing the bond wave dynamics. Engineering the continuous wave dynamics and influencing parameters are both key for optimum post-bond overlay accuracy. Any wafer stress will result into distortion of patterns and additional misalignment term. Despite typical distortion values are well below 50nm already, further optimization of both wafer bonding as well as wafer preparation and preprocessing are key for hybrid and monolithic integration.

Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects

As the density of 3D interconnects is increasing exponentially when scaling to lower levels of the interconnect wiring, in most cases 3D interconnect pitches of 5 μm and below will be required. Dielectric wafer to wafer bonding with via last integration can offer these interconnect densities. Wafer-to-wafer alignment and its impact on via last alignment are discussed. By taking into account current alignment tolerances, via last diameters of 1μm enable 2μm pitch TSV interconnection densities. For further scaling the TSV pitch, lower wafer to wafer bonding alignment tolerance are required. Today the best wafer-to-wafer overlay accuracy is around 400nm, but developments are ongoing to reduce this tolerance further to 200nm.

Thin WLFO and based WLSiP enabling WL3D, realized using Temporary Reconstituted Panel Bonding Technology

The interest in FOWLP as new flexible packaging technology platform is continuously increasing. High volume capability is proven for configurations with single die (WLFO), multi-die side-by-side, partially with discrete passives integration (WLMCM and WLSiP), both with single sided single and multiple RDL layers. The next step to achieve higher integration density, e.g. for mobile and IoT applications, is to go in the third dimension (WL3D/WLPoP) with total package thickness below 1mm, targeting 0.8mm and even less in the next development step. High design flexibility, superior performance and small form-factor in x and y, but even more important in z-dimension, are the essential packaging characteristics required for this type of smart system integration. The eWLB based WLFO technology platform of NANIUM promises to deliver all of those requirements. While previous generations of WLFO packages only consisted of one plane of single or multiple RDL layers (frontside RDL at BGA side), recent evolutions enab...

Critical Process Parameters And Failure Analysis For Temporary Bonded Wafer Stacks

Temporary bonding is a ley process for almost any 3D integration scheme. It offers not only more stability during the thinning process but also allows handling for backside processing of thin wafers like interposers during subsequent process steps [1–2]. Although the temporary bonding technology is already used in high volume manufacturing and has proven high yield process, nevertheless, some limitation appears for some specific applications [3-4-5]. One critical failure origin is delamination, which can lead to wafer breakage and therefore yield loss. This separation of the device wafer and the carrier wafer typically occurs when the temporary bonded wafer stack (device wafer, carrier wafer and temporary bonding adhesive in between) experiences further processing done under high temperature and low vacuum like PECVD deposition. Further insight into processing parameters and a better understanding of the key contributing factors as well as its dependencies help to prevent this failure. To investigate the ...

Heterogeneous integration through direct wafer bonding

Recent developments in direct wafer bonding make this technology a versatile tool for heterogeneous integration. Advances in process flows and equipment technology trigger new types of application schemes for novel types of device architecture.

Temporary bonding on the move towards high volume: A status update on cost-of-ownership

The ability to process thin wafers with thicknesses of 20-50um on front- and back side is a key technology for 3D stacked ICs (3Ds-IC). The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld consumer devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. Consensus has developed on the use of temporary bonding and debonding technology as the solution of choice for reliably handling thin wafers through back side processing steps. Temporary bonding and debonding comprises several processes for which yield is essential, as costly fully functional device wafers are being processed. The temporary bonding process yield has a major impact on the overall Cost of Ownership (CoO). On the other hand, throughput of the individual process steps like spin coating, bonding, cure, debonding and cleaning processes is the second determining factor for improved CoO. This paper should provide in depth understanding of CoO contributors to temporary bonding and debonding. Focus is put on the cost sensitivity of the major influencing contributor to temporary bond as well as debonding.

Versatile thin wafer stacking technology for monolithic integration of temporary bonded thin wafers

This paper will focus on recent results for wafer stacking of temporary bonded wafers for the integration in a monolithic device process. For ease of process integration, this process enables the face-to-back stacking of several device layers. Plasma activated fusion bonding could be shown to be an enabling step to lower annealing temperatures into a CMOS compatible range. Furthermore, plasma activation enables to use thermoplastic adhesives. Two types of test vehicles have been fabricated, showing on the one hand a successful stacking of a 11μm thin device wafer onto another thick substrate wafers. On the other hand, a triple stack of thick substrate wafer and two 20μm thin devices is shown as well. Bonding results have been measured using state-of-the-art measurement techniques, such as infrared scanning, scanning acoustic microscopy and scanning white light interferometry, to detect interface defects, bond integrity and temporary adhesive properties, respectively.