Jürgen Dr. Holz

MOS transistor reliability under analog operation

Abstract Reliability evaluation for MOS transistors under analog operation requires different or specifically adapted approaches compared to the ones known from the digital world. Focussing on the particular analog operating conditions and the related lifetime criteria, a comprehensive discussion is performed of MOSFET reliability taking into account channel hot-carrier stress, bias temperature instabilities, and oxide wear-out. The conditions for the occurrence of these mechanisms and criteria for stress induced malfunction of analog circuits are discussed and the physics behind the behavior of typical analog device parameters after stress are addressed. Furthermore, specific aspects concerning the definition of analog lifetime criteria and strategies to guarantee reliability by means of circuit design are considered.

Trapping mechanisms in negative bias temperature stressed p-MOSFETs

Abstract Device parameter degradation of p-MOSFETs after N egative B ias T emperature Stress (NBTS) and the related charge trapping mechanisms are investigated in detail. Applying specific annealing experiments to NBT-stressed transistors, the influence of stress-induced oxide charge build-up and interface state generation on the degradation of the electrical parameters is evaluated. It is found, that hole trapping significantly contributes to the NBTS-induced Vt shift. Furthermore, experimental results of the hot-carrier behavior of virgin and NBT-stressed devices demonstrate that only weak correlations between these types of stress and the involved degradation mechanisms exist, which is important in applications with alternating stress situations.