Jyun-Siang Huang

Source/Drain dopant concentration induced reliability issues in charge trapping NAND flash cells

Source/Drain (S/D) dopant concentration related reliability issues including erase speed degradation, sub-threshold swing (SS) increase, and program/erase (P/E) cycling induced low threshold voltage (VT) state drift and on-state current (ION) reduction are carefully examined in charge trapping (CT) NAND flash memories. Residual charges above S/D junctions has been identified as a dominant factor and cell performances are greatly improved with increasing S/D dosages. Moreover, a new program disturbance behavior, which possibly originates from junction leakage or breakdown induced hot carriers injection, is observed. Simulation results confirm that a high lateral junction field occurs at a program-disturbed cell once its S/D is fully depleted. Although optimizing S/D dosage can ease this situation, it is still a possible obstacle for further device scaling.

A Novel Low-Voltage Low-Power Programming Method for NAND Flash Cell by Utilizing Self-Boosting Channel Potential for Carrier Heating

A novel low-voltage low-power programming method for NAND Flash cell is presented. By utilizing the self-channel boosting technique, a sufficiently high local field is established in a NAND string that causes efficient hot-carrier injection. This method has been successfully demonstrated in the 75-nm-node floating-gate NAND cells, along with comprehensive studies on bias and timing effects. Requirements for high-voltage supporting devices, circuitry, and process in conventional Fowler-Nordheim programmed NAND cells are greatly mitigated. It would be very attractive for scaled NAND Flash technology in the future.

A Highly Punchthrough-Immune Array Architecture and Program Method for Floating-Gate NOR-Type Nonvolatile Memory

A novel array architecture is proposed for floating-gate nor-type nonvolatile memory cells. By embedding a floating n+ region between two cells in each memory pair, punchthrough (PT) immunity is greatly improved. Since the operating cell and the cascade cell belong to two independent word-lines, bit-pattern effect on read and program characteristics is mitigated, and multilevel-cell storage can be easily realized. No additional program disturb has been found. Erase, endurance, and retention characteristics are comparable with its conventional counterpart. According to simulations, Lg as short as 56 nm, which is projected to serve for 28 nm technology node, is feasible without suffering a serious PT effect.

A highly punchthrough-immune operation method for an ultra-short-channel hot-carrier-injection type non-volatile memory cell

A novel bias scheme is proposed for non-volatile memory cells arranged in a virtual-ground array that utilizes hot-carrier injections for program and erase operations. By taking two adjacent cells on the same wordline as a unit, and letting the commonly shared n+ region being floating during program and erase, punchthrough immunity is greatly improved. Program/erase speed, endurance, and retention characteristics are comparable to conventional operations. NBit cell is projected to be workable at sub-40 nm node by such scheme.

A Novel Trapping-Nitride-Storage Non-Volatile Memory Cell Using a Gated-Diode Structure With an Ultra-Thin Dielectric Dopant Diffusion Barrier

A novel trapping-nitride-storage nonvolatile memory cell by using a gated-diode structure is proposed. An ultrathin nitride layer is introduced between the n-type and p-type regions of the diode. This layer acts as a dopant diffusion barrier that well defines the junction location. Meanwhile, it is thin enough that charge carriers can flow through it via direct tunneling at low field as being sensed. Good program/erase characteristics and acceptable reliability are presented. Finally, using a low-bandgap material to enhance the sensing current is suggested along with the preferred device structure.

A simulation study of the bit interference effects in an ultra-thin-body, double-gate, trapped-charge-storage type non-volatile memory cell

Bit interference effects in an ultra-thin body, double-gate, trapped-charge-storage type non-volatile memory cell are investigated through two-dimensional device simulations. Though such device is more scalable and has a larger current drive, it is found that the bit states on the two sides of the ldquocommonrdquo body would interact with each other if the body is too thin. The remote charge effect, the remote punch-through effect, and the suppressed read-through capability are clarified to be the major killing factors. If there is a higher intrinsic-Vt along the cellpsilas channel beyond the active thin-body regions, part of the created memory window will be shadowed. Such interferences would become the worst as these cells are arranged in an array having the common-gate feature.